top Project Status (02/13/2015 - 15:49:51)
Project File: Thermisotor_DS18B20.xise Parser Errors: No Errors
Module Name: top Implementation State: Programming File Generated
Target Device: xc6slx9-2tqg144
  • Errors:
No Errors
Product Version:ISE 14.2
  • Warnings:
37 Warnings (3 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
X 1 Failing Constraint
Environment: System Settings
  • Final Timing Score:
754616  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 168 11,440 1%  
    Number used as Flip Flops 168      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 1,629 5,720 28%  
    Number used as logic 1,623 5,720 28%  
        Number using O6 output only 1,424      
        Number using O5 output only 63      
        Number using O5 and O6 136      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
    Number used exclusively as route-thrus 6      
        Number with same-slice register load 0      
        Number with same-slice carry load 6      
        Number with other load 0      
Number of occupied Slices 485 1,430 33%  
Nummber of MUXCYs used 308 2,860 10%  
Number of LUT Flip Flop pairs used 1,636      
    Number with an unused Flip Flop 1,496 1,636 91%  
    Number with an unused LUT 7 1,636 1%  
    Number of fully used LUT-FF pairs 133 1,636 8%  
    Number of unique control sets 19      
    Number of slice register sites lost
        to control set restrictions
64 11,440 1%  
Number of bonded IOBs 4 102 3%  
    Number of LOCed IOBs 4 4 100%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 2 16 12%  
    Number used as BUFGs 2      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 1 4 25%  
    Number used as DCMs 1      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 0 200 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 1 16 6%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.85      
 
Performance Summary [-]
Final Timing Score: 754616 (Setup: 754616, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 1 Failing Constraint    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent±Ý 2 13 15:47:14 2015033 Warnings (3 new)1 Info (0 new)
Translation ReportCurrent±Ý 2 13 15:47:19 2015001 Info (0 new)
Map ReportCurrent±Ý 2 13 15:47:47 2015008 Infos (0 new)
Place and Route ReportCurrent±Ý 2 13 15:49:32 201504 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportCurrent±Ý 2 13 15:49:37 2015003 Infos (0 new)
Bitgen ReportCurrent±Ý 2 13 15:49:45 2015001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrent±Ý 2 13 15:49:46 2015
WebTalk Log FileCurrent±Ý 2 13 15:49:51 2015

Date Generated: 02/13/2015 - 15:49:51