Release 14.2 - xst P.28xd (nt64) Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.09 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.09 secs --> Reading design: top.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Parsing 3) HDL Elaboration 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Partition Report 8) Design Summary 8.1) Primitive and Black Box Usage 8.2) Device utilization summary 8.3) Partition Resource Summary 8.4) Timing Report 8.4.1) Clock Information 8.4.2) Asynchronous Control Signals Information 8.4.3) Timing Summary 8.4.4) Timing Details 8.4.5) Cross Clock Domains Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "top.prj" Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "top" Output Format : NGC Target Device : xc6slx9-2-tqg144 ---- Source Options Top Module Name : top Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : LUT RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Shift Register Extraction : YES ROM Style : Auto Resource Sharing : YES Asynchronous To Synchronous : NO Shift Register Minimum Size : 2 Use DSP Block : Auto Automatic Register Balancing : No ---- Target Options LUT Combining : Auto Reduce Control Sets : Auto Add IO Buffers : YES Global Maximum Fanout : 100000 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Optimize Instantiated Primitives : NO Use Clock Enable : Auto Use Synchronous Set : Auto Use Synchronous Reset : Auto Pack IO Registers into IOBs : Auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Power Reduction : NO Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 DSP48 Utilization Ratio : 100 Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Parsing * ========================================================================= Analyzing Verilog file "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Thermisotor_DS18B20\hextobcd.v" into library work Parsing module . Analyzing Verilog file "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Thermisotor_DS18B20\Printf.v" into library work Parsing module . Analyzing Verilog file "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Thermisotor_DS18B20\DS18B20.v" into library work Parsing module . Analyzing Verilog file "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Thermisotor_DS18B20\top.v" into library work Parsing module . ========================================================================= * HDL Elaboration * ========================================================================= WARNING:HDLCompiler:1016 - "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Thermisotor_DS18B20\top.v" Line 38: Port CLK180 is not connected to this instance Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Thermisotor_DS18B20\top.v". Found 1-bit register for signal . Found 2-bit register for signal . Found 2-bit adder for signal created at line 64. Summary: inferred 1 Adder/Subtractor(s). inferred 3 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Thermisotor_DS18B20\Printf.v". CLOCKS_PER_BIT = 2604 CLOCKS_WAIT_FOR_RECEIVE = 1302 MAX_TX_BIT_COUNT = 9 MAX_DATA_BUFFER_INDEX = 15 LCD_BLANK = 8'b00100000 LCD_DASH = 8'b00101101 LCD_COLON = 8'b00111010 LCD_PERIODE = 8'b00101110 LCD_EQUAL = 8'b00111101 LCD_0 = 8'b00110000 LCD_1 = 8'b00110001 LCD_2 = 8'b00110010 LCD_3 = 8'b00110011 LCD_4 = 8'b00110100 LCD_5 = 8'b00110101 LCD_6 = 8'b00110110 LCD_7 = 8'b00110111 LCD_8 = 8'b00111000 LCD_9 = 8'b00111001 LCD_A = 8'b01000001 LCD_B = 8'b01000010 LCD_C = 8'b01000011 LCD_D = 8'b01000100 LCD_E = 8'b01000101 LCD_F = 8'b01000110 LCD_G = 8'b01000111 LCD_H = 8'b01001000 LCD_I = 8'b01001001 LCD_J = 8'b01001010 LCD_K = 8'b01001011 LCD_L = 8'b01001100 LCD_M = 8'b01001101 LCD_N = 8'b01001110 LCD_O = 8'b01001111 LCD_P = 8'b01010000 LCD_Q = 8'b01010001 LCD_R = 8'b01010010 LCD_S = 8'b01010011 LCD_T = 8'b01010100 LCD_U = 8'b01010101 LCD_V = 8'b01010110 LCD_W = 8'b01010111 LCD_X = 8'b01011000 LCD_Y = 8'b01011001 LCD_Z = 8'b01011010 LCD_UNDER = 8'b01011111 LCD_S_a = 8'b01100001 LCD_S_b = 8'b01100010 LCD_S_c = 8'b01100011 LCD_S_d = 8'b01100100 LCD_S_e = 8'b01100101 LCD_S_f = 8'b01100110 LCD_S_g = 8'b01100111 LCD_S_h = 8'b01101000 LCD_S_i = 8'b01101001 LCD_S_j = 8'b01101010 LCD_S_k = 8'b01101011 LCD_S_l = 8'b01101100 LCD_S_m = 8'b01101101 LCD_S_n = 8'b01101110 LCD_S_o = 8'b01101111 LCD_S_p = 8'b01110000 LCD_S_q = 8'b01110001 LCD_S_r = 8'b01110010 LCD_S_s = 8'b01110011 LCD_S_t = 8'b01110100 LCD_S_u = 8'b01110101 LCD_S_v = 8'b01110110 LCD_S_w = 8'b01110111 LCD_S_x = 8'b01111000 LCD_S_y = 8'b01111001 LCD_S_z = 8'b01111010 LCD_dot = 8'b01100000 Found 4-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 19-bit register for signal . Found 8-bit register for signal . Found 16-bit register for signal . Found 4-bit adder for signal created at line 170. Found 8-bit adder for signal created at line 174. Found 16-bit adder for signal created at line 185. Found 19-bit adder for signal created at line 188. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 3-bit subtractor for signal > created at line 169. Found 1-bit 8-to-1 multiplexer for signal created at line 169. Found 19-bit comparator greater for signal created at line 156 Found 4-bit comparator greater for signal created at line 168 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Summary: inferred 25 Adder/Subtractor(s). inferred 56 D-type flip-flop(s). inferred 12 Comparator(s). inferred 17 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Thermisotor_DS18B20\hextobcd.v". Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 3-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Summary: inferred 252 Adder/Subtractor(s). inferred 252 Comparator(s). inferred 981 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Thermisotor_DS18B20\DS18B20.v". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 16-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 32-bit register for signal . Found 16-bit register for signal . Found 8-bit register for signal . Found 4-bit register for signal . Found 8-bit register for signal . Found 4-bit register for signal . Found 8-bit register for signal . Found finite state machine for signal . ----------------------------------------------------------------------- | States | 34 | | Transitions | 87 | | Inputs | 17 | | Outputs | 40 | | Clock | clk_main (rising_edge) | | Power Up State | 00000000 | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 32-bit adder for signal created at line 64. Found 16-bit adder for signal created at line 83. Found 8-bit adder for signal created at line 199. Found 4-bit adder for signal created at line 205. Found 8-bit adder for signal created at line 304. Found 4-bit adder for signal created at line 310. Found 16x10-bit multiplier for signal created at line 338. Found 4x8-bit Read Only RAM for signal <_n0613> Found 1-bit tristate buffer for signal created at line 340 Found 16-bit comparator greater for signal created at line 78 Found 16-bit comparator greater for signal created at line 92 Found 16-bit comparator greater for signal created at line 154 Found 8-bit comparator greater for signal created at line 192 Found 16-bit comparator greater for signal created at line 271 Found 16-bit comparator greater for signal created at line 288 Found 4-bit comparator greater for signal created at line 323 Summary: inferred 1 RAM(s). inferred 1 Multiplier(s). inferred 6 Adder/Subtractor(s). inferred 122 D-type flip-flop(s). inferred 7 Comparator(s). inferred 25 Multiplexer(s). inferred 1 Tristate(s). inferred 1 Finite State Machine(s). Unit synthesized. Synthesizing Unit . Related source file is "". Found 36-bit adder for signal created at line 0. Found 35-bit adder for signal created at line 0. Found 34-bit adder for signal created at line 0. Found 33-bit adder for signal created at line 0. Found 32-bit adder for signal created at line 0. Found 31-bit adder for signal created at line 0. Found 30-bit adder for signal created at line 0. Found 29-bit adder for signal created at line 0. Found 28-bit adder for signal created at line 0. Found 27-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 26-bit adder for signal created at line 0. Found 36-bit comparator lessequal for signal created at line 0 Found 35-bit comparator lessequal for signal created at line 0 Found 34-bit comparator lessequal for signal created at line 0 Found 33-bit comparator lessequal for signal created at line 0 Found 32-bit comparator lessequal for signal created at line 0 Found 31-bit comparator lessequal for signal created at line 0 Found 30-bit comparator lessequal for signal created at line 0 Found 29-bit comparator lessequal for signal created at line 0 Found 28-bit comparator lessequal for signal created at line 0 Found 27-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Found 26-bit comparator lessequal for signal created at line 0 Summary: inferred 26 Adder/Subtractor(s). inferred 27 Comparator(s). inferred 601 Multiplexer(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # RAMs : 1 4x8-bit single-port Read Only RAM : 1 # Multipliers : 1 16x10-bit multiplier : 1 # Adders/Subtractors : 310 16-bit adder : 2 19-bit adder : 1 2-bit adder : 1 26-bit adder : 16 27-bit adder : 1 28-bit adder : 1 29-bit adder : 1 3-bit subtractor : 1 30-bit adder : 1 31-bit adder : 1 32-bit adder : 2 33-bit adder : 1 34-bit adder : 1 35-bit adder : 1 36-bit adder : 1 4-bit adder : 255 7-bit adder : 20 8-bit adder : 3 # Registers : 21 1-bit register : 4 16-bit register : 3 19-bit register : 1 2-bit register : 1 32-bit register : 1 4-bit register : 3 8-bit register : 8 # Comparators : 298 16-bit comparator greater : 5 19-bit comparator greater : 1 26-bit comparator lessequal : 17 27-bit comparator lessequal : 1 28-bit comparator lessequal : 1 29-bit comparator lessequal : 1 3-bit comparator greater : 1 30-bit comparator lessequal : 1 31-bit comparator lessequal : 1 32-bit comparator lessequal : 1 33-bit comparator lessequal : 1 34-bit comparator lessequal : 1 35-bit comparator lessequal : 1 36-bit comparator lessequal : 1 4-bit comparator greater : 253 4-bit comparator lessequal : 10 8-bit comparator greater : 1 # Multiplexers : 1624 1-bit 2-to-1 multiplexer : 1582 1-bit 8-to-1 multiplexer : 1 16-bit 2-to-1 multiplexer : 14 19-bit 2-to-1 multiplexer : 1 26-bit 2-to-1 multiplexer : 3 4-bit 2-to-1 multiplexer : 4 40-bit 2-to-1 multiplexer : 1 8-bit 2-to-1 multiplexer : 18 # Tristates : 1 1-bit tristate buffer : 1 # FSMs : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 4-word x 8-bit | | | weA | connected to signal | high | | addrA | connected to signal > | | | diA | connected to signal | | | doA | connected to internal node | | ----------------------------------------------------------------------- Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . Unit synthesized (advanced). ========================================================================= Advanced HDL Synthesis Report Macro Statistics # RAMs : 1 4x8-bit single-port distributed Read Only RAM : 1 # Multipliers : 1 16x10-bit multiplier : 1 # Adders/Subtractors : 303 16-bit adder : 1 26-bit adder : 26 3-bit adder : 24 3-bit subtractor : 1 4-bit adder : 229 7-bit adder : 20 8-bit adder : 2 # Counters : 8 16-bit up counter : 1 19-bit up counter : 1 2-bit up counter : 1 32-bit up counter : 1 4-bit up counter : 2 8-bit up counter : 2 # Registers : 88 Flip-Flops : 88 # Comparators : 298 16-bit comparator greater : 5 19-bit comparator greater : 1 26-bit comparator lessequal : 17 27-bit comparator lessequal : 1 28-bit comparator lessequal : 1 29-bit comparator lessequal : 1 3-bit comparator greater : 1 30-bit comparator lessequal : 1 31-bit comparator lessequal : 1 32-bit comparator lessequal : 1 33-bit comparator lessequal : 1 34-bit comparator lessequal : 1 35-bit comparator lessequal : 1 36-bit comparator lessequal : 1 4-bit comparator greater : 253 4-bit comparator lessequal : 10 8-bit comparator greater : 1 # Multiplexers : 1620 1-bit 2-to-1 multiplexer : 1582 1-bit 8-to-1 multiplexer : 1 16-bit 2-to-1 multiplexer : 13 26-bit 2-to-1 multiplexer : 3 4-bit 2-to-1 multiplexer : 2 40-bit 2-to-1 multiplexer : 1 8-bit 2-to-1 multiplexer : 18 # FSMs : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with one-hot encoding. ------------------------------------------------ State | Encoding ------------------------------------------------ 00000000 | 0000000000000000000000000000000001 00000001 | 0000000000000000000000000000000010 00000010 | 0000000000000000000000000000000100 00000011 | 0000000000000000000000000000001000 00011111 | 0000000000000000000000000000010000 00100000 | 0000000000000000000000000000100000 00000110 | 0000000000000000000000000001000000 00000111 | 0000000000000000000000000010000000 00001000 | 0000000000000000000000000100000000 00001001 | 0000000000000000000000001000000000 00001010 | 0000000000000000000000010000000000 00001011 | 0000000000000000000000100000000000 00001100 | 0000000000000000000001000000000000 00011101 | 0000000000000000000010000000000000 00001110 | 0000000000000000000100000000000000 00001111 | 0000000000000000001000000000000000 00011100 | 0000000000000000010000000000000000 00011011 | 0000000000000000100000000000000000 00100001 | 0000000000000001000000000000000000 00010110 | 0000000000000010000000000000000000 00010111 | 0000000000000100000000000000000000 00010000 | 0000000000001000000000000000000000 00011000 | 0000000000010000000000000000000000 00011001 | 0000000000100000000000000000000000 00011010 | 0000000001000000000000000000000000 00011110 | 0000000010000000000000000000000000 00001101 | 0000000100000000000000000000000000 00000100 | 0000001000000000000000000000000000 00000101 | 0000010000000000000000000000000000 00100010 | 0000100000000000000000000000000000 00100011 | 0001000000000000000000000000000000 00100100 | 0010000000000000000000000000000000 00100101 | 0100000000000000000000000000000000 00010101 | 1000000000000000000000000000000000 ------------------------------------------------ WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 19. Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 168 Flip-Flops : 168 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Design Summary * ========================================================================= Top Level Output File Name : top.ngc Primitive and Black Box Usage: ------------------------------ # BELS : 2298 # GND : 1 # INV : 17 # LUT1 : 69 # LUT2 : 122 # LUT3 : 109 # LUT4 : 119 # LUT5 : 363 # LUT6 : 919 # MUXCY : 259 # MUXF7 : 58 # VCC : 1 # XORCY : 261 # FlipFlops/Latches : 168 # FD : 37 # FDE : 87 # FDR : 1 # FDRE : 43 # Clock Buffers : 2 # BUFG : 2 # IO Buffers : 3 # IBUFG : 1 # IOBUF : 1 # OBUF : 1 # DCMs : 1 # DCM_SP : 1 # DSPs : 1 # DSP48A1 : 1 Device utilization summary: --------------------------- Selected Device : 6slx9tqg144-2 Slice Logic Utilization: Number of Slice Registers: 168 out of 11440 1% Number of Slice LUTs: 1718 out of 5720 30% Number used as Logic: 1718 out of 5720 30% Slice Logic Distribution: Number of LUT Flip Flop pairs used: 1731 Number with an unused Flip Flop: 1563 out of 1731 90% Number with an unused LUT: 13 out of 1731 0% Number of fully used LUT-FF pairs: 155 out of 1731 8% Number of unique control sets: 19 IO Utilization: Number of IOs: 4 Number of bonded IOBs: 3 out of 102 2% Specific Feature Utilization: Number of BUFG/BUFGCTRLs: 2 out of 16 12% Number of DSP48A1s: 1 out of 16 6% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= Timing Report NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ osc | DCM_SP:CLKFX | 169 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -2 Minimum period: 51.364ns (Maximum Frequency: 19.469MHz) Minimum input arrival time before clock: 3.735ns Maximum output required time after clock: 4.162ns Maximum combinational path delay: No path found Timing Details: --------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'osc' Clock period: 51.364ns (frequency: 19.469MHz) Total number of paths / destination ports: 794792489880982520000 / 359 ------------------------------------------------------------------------- Delay: 51.364ns (Levels of Logic = 48) Source: DS18B20/Mmult_temp_sum[15]_PWR_7_o_MuLt_148_OUT (DSP) Destination: Printf/data_tx_2 (FF) Source Clock: osc rising Destination Clock: osc rising Data Path: DS18B20/Mmult_temp_sum[15]_PWR_7_o_MuLt_148_OUT to Printf/data_tx_2 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ DSP48A1:CLK->M19 53 4.371 1.844 DS18B20/Mmult_temp_sum[15]_PWR_7_o_MuLt_148_OUT (DS18B20/temp_sum[15]_PWR_7_o_MuLt_148_OUT<19>) LUT2:I1->O 8 0.254 1.052 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<16>1_SW0 (N41) LUT6:I4->O 1 0.250 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<15>11_1_G (N3065) MUXF7:I1->O 8 0.175 0.943 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<15>11_1 (DS18B20/temp_sum[15]_PWR_7_o_div_149/o<15>11) MUXF7:S->O 28 0.185 1.453 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mmux_a[0]_a[25]_MUX_1967_o1141 (DS18B20/temp_sum[15]_PWR_7_o_div_149/Madd_a[25]_GND_7_o_add_25_OUT_lut<22>) LUT6:I5->O 21 0.254 1.538 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mmux_a[0]_a[25]_MUX_1993_o114 (DS18B20/temp_sum[15]_PWR_7_o_div_149/Madd_a[25]_GND_7_o_add_27_OUT_lut<22>) LUT5:I2->O 3 0.235 0.766 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<13>1_1 (DS18B20/temp_sum[15]_PWR_7_o_div_149/o<13>1) LUT6:I5->O 17 0.254 1.209 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mmux_a[0]_a[25]_MUX_2019_o113 (DS18B20/temp_sum[15]_PWR_7_o_div_149/Madd_a[25]_GND_7_o_add_29_OUT_lut<21>) LUT4:I3->O 16 0.254 1.182 DS18B20/temp_sum[15]_PWR_7_o_div_149/Madd_a[25]_GND_7_o_add_29_OUT_cy<22>11 (DS18B20/temp_sum[15]_PWR_7_o_div_149/Madd_a[25]_GND_7_o_add_29_OUT_cy<22>) LUT6:I5->O 1 0.254 0.682 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mmux_a[0]_a[25]_MUX_2045_o171_1 (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mmux_a[0]_a[25]_MUX_2045_o1711) LUT6:I5->O 7 0.254 0.910 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<11>13_SW8 (N559) LUT6:I5->O 6 0.254 1.104 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mmux_a[0]_a[25]_MUX_2071_o1151 (DS18B20/temp_sum[15]_PWR_7_o_div_149/a[23]_a[25]_MUX_2048_o) LUT6:I3->O 12 0.235 1.069 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<10>21_SW3 (N770) LUT6:I5->O 12 0.254 1.499 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mmux_a[0]_a[25]_MUX_2097_o1161 (DS18B20/temp_sum[15]_PWR_7_o_div_149/a[24]_a[25]_MUX_2073_o) LUT5:I0->O 9 0.254 0.976 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<9>21_SW2_SW0 (N2403) LUT6:I5->O 7 0.254 0.910 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<9>23_1 (DS18B20/temp_sum[15]_PWR_7_o_div_149/o<9>23) LUT6:I5->O 2 0.254 0.726 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<8>22_1 (DS18B20/temp_sum[15]_PWR_7_o_div_149/o<8>22) LUT5:I4->O 12 0.254 1.069 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<7>23_SW0 (N340) LUT6:I5->O 15 0.254 1.155 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<7>23 (DS18B20/temp_sum[15]_PWR_7_o_div_149/o<7>22) LUT6:I5->O 5 0.254 0.840 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<7>25_1 (DS18B20/temp_sum[15]_PWR_7_o_div_149/o<7>25) MUXF7:S->O 35 0.185 1.570 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<6>23 (DS18B20/temp_sum[15]_PWR_7_o_div_149/o<6>22) LUT6:I5->O 8 0.254 1.172 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mmux_a[0]_a[25]_MUX_2201_o171 (DS18B20/temp_sum[15]_PWR_7_o_div_149/a[16]_a[25]_MUX_2185_o) LUT6:I3->O 19 0.235 1.261 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<5>26_SW2_SW0 (N1212) LUT6:I5->O 6 0.254 0.876 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<5>26_1 (DS18B20/temp_sum[15]_PWR_7_o_div_149/o<5>26) LUT6:I5->O 1 0.254 0.910 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<4>35_SW0_1 (DS18B20/temp_sum[15]_PWR_7_o_div_149/o<4>35_SW0) LUT6:I3->O 13 0.235 1.097 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<4>35_1 (DS18B20/temp_sum[15]_PWR_7_o_div_149/o<4>35) MUXF7:S->O 44 0.185 1.721 DS18B20/temp_sum[15]_PWR_7_o_div_149/o<3>31 (DS18B20/temp_sum[15]_PWR_7_o_div_149/o<3>3) LUT6:I5->O 3 0.254 1.196 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mmux_n1829261 (DS18B20/temp_sum[15]_PWR_7_o_div_149/n1829<9>) LUT5:I0->O 1 0.254 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<2>_lut<0> (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<2>_lut<0>) MUXCY:S->O 1 0.215 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<2>_cy<0> (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<2>_cy<0>) MUXCY:CI->O 1 0.023 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<2>_cy<1> (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<2>_cy<1>) MUXCY:CI->O 1 0.023 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<2>_cy<2> (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<2>_cy<2>) MUXCY:CI->O 1 0.023 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<2>_cy<3> (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<2>_cy<3>) MUXCY:CI->O 75 0.235 2.015 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<2>_cy<4> (PrintfData1<2>) LUT5:I4->O 2 0.254 1.156 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mmux_n1833251 (DS18B20/temp_sum[15]_PWR_7_o_div_149/n1833<8>) LUT5:I0->O 1 0.254 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<1>_lut<0> (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<1>_lut<0>) MUXCY:S->O 1 0.215 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<1>_cy<0> (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<1>_cy<0>) MUXCY:CI->O 1 0.023 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<1>_cy<1> (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<1>_cy<1>) MUXCY:CI->O 1 0.023 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<1>_cy<2> (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<1>_cy<2>) MUXCY:CI->O 1 0.023 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<1>_cy<3> (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<1>_cy<3>) MUXCY:CI->O 32 0.235 1.520 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<1>_cy<4> (PrintfData1<1>) LUT5:I4->O 2 0.254 1.156 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mmux_n1728241 (DS18B20/temp_sum[15]_PWR_7_o_div_149/n1728<7>) LUT5:I0->O 1 0.254 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<0>_lut<0> (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<0>_lut<0>) MUXCY:S->O 1 0.215 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<0>_cy<0> (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<0>_cy<0>) MUXCY:CI->O 1 0.023 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<0>_cy<1> (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<0>_cy<1>) MUXCY:CI->O 1 0.023 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<0>_cy<2> (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<0>_cy<2>) MUXCY:CI->O 1 0.023 0.000 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<0>_cy<3> (DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<0>_cy<3>) MUXCY:CI->O 3 0.235 0.766 DS18B20/temp_sum[15]_PWR_7_o_div_149/Mcompar_o<0>_cy<4> (PrintfData1<0>) LUT6:I5->O 1 0.254 0.000 Printf/data_buffer_index[4]_X_3_o_wide_mux_5_OUT<0>7 (Printf/data_buffer_index[4]_X_3_o_wide_mux_5_OUT<0>) FDE:D 0.074 Printf/data_tx_0 ---------------------------------------- Total 51.364ns (14.021ns logic, 37.343ns route) (27.3% logic, 72.7% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'osc' Total number of paths / destination ports: 11 / 11 ------------------------------------------------------------------------- Offset: 3.735ns (Levels of Logic = 2) Source: Thermistor (PAD) Destination: DS18B20/retd_7 (FF) Destination Clock: osc rising Data Path: Thermistor to DS18B20/retd_7 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IOBUF:IO->O 4 1.328 0.912 Thermistor_IOBUF (N51) LUT4:I2->O 8 0.250 0.943 DS18B20/state__n1413_inv1 (DS18B20/_n1413_inv) FDE:CE 0.302 DS18B20/retd_0 ---------------------------------------- Total 3.735ns (1.880ns logic, 1.855ns route) (50.3% logic, 49.7% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'osc' Total number of paths / destination ports: 3 / 2 ------------------------------------------------------------------------- Offset: 4.162ns (Levels of Logic = 1) Source: DS18B20/Thermistor_r (FF) Destination: Thermistor (PAD) Source Clock: osc rising Data Path: DS18B20/Thermistor_r to Thermistor Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 2 0.525 0.725 DS18B20/Thermistor_r (DS18B20/Thermistor_r) IOBUF:I->IO 2.912 Thermistor_IOBUF (Thermistor) ---------------------------------------- Total 4.162ns (3.437ns logic, 0.725ns route) (82.6% logic, 17.4% route) ========================================================================= Cross Clock Domains Report: -------------------------- Clock to Setup on destination clock osc ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ osc | 51.364| | | | ---------------+---------+---------+---------+---------+ ========================================================================= Total REAL time to Xst completion: 38.00 secs Total CPU time to Xst completion: 37.85 secs --> Total memory usage is 320588 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 33 ( 0 filtered) Number of infos : 1 ( 0 filtered)