xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.syr" 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.syr" 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.syr" 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.syr" 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.syr" 
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc top.ucf -p xc6slx9-tqg144-2 LCD.ngc LCD.ngd  
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.syr" 
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc top.ucf -p xc6slx9-tqg144-2 LCD.ngc LCD.ngd  
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.syr" 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.syr" 
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc top.ucf -p xc6slx9-tqg144-2 LCD.ngc LCD.ngd  
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o LCD_map.ncd LCD.ngd LCD.pcf 
par -w -intstyle ise -ol high -mt off LCD_map.ncd LCD.ncd LCD.pcf 
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml LCD.twx LCD.ncd -o LCD.twr LCD.pcf -ucf top.ucf 
bitgen -intstyle ise -f LCD.ut LCD.ncd 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.syr" 
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc top.ucf -p xc6slx9-tqg144-2 LCD.ngc LCD.ngd  
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o LCD_map.ncd LCD.ngd LCD.pcf 
par -w -intstyle ise -ol high -mt off LCD_map.ncd LCD.ncd LCD.pcf 
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml LCD.twx LCD.ncd -o LCD.twr LCD.pcf -ucf top.ucf 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.syr" 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.syr" 
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc top.ucf -p xc6slx9-tqg144-2 LCD.ngc LCD.ngd  
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o LCD_map.ncd LCD.ngd LCD.pcf 
par -w -intstyle ise -ol high -mt off LCD_map.ncd LCD.ncd LCD.pcf 
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml LCD.twx LCD.ncd -o LCD.twr LCD.pcf -ucf top.ucf 
bitgen -intstyle ise -f LCD.ut LCD.ncd 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.syr" 
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc top.ucf -p xc6slx9-tqg144-2 LCD.ngc LCD.ngd  
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o LCD_map.ncd LCD.ngd LCD.pcf 
par -w -intstyle ise -ol high -mt off LCD_map.ncd LCD.ncd LCD.pcf 
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml LCD.twx LCD.ncd -o LCD.twr LCD.pcf -ucf top.ucf 
bitgen -intstyle ise -f LCD.ut LCD.ncd 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.syr" 
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc top.ucf -p xc6slx9-tqg144-2 LCD.ngc LCD.ngd  
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o LCD_map.ncd LCD.ngd LCD.pcf 
par -w -intstyle ise -ol high -mt off LCD_map.ncd LCD.ncd LCD.pcf 
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml LCD.twx LCD.ncd -o LCD.twr LCD.pcf -ucf top.ucf 
bitgen -intstyle ise -f LCD.ut LCD.ncd 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/TextLCD_16by2/LCD.syr" 
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc top.ucf -p xc6slx9-tqg144-2 LCD.ngc LCD.ngd  
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o LCD_map.ncd LCD.ngd LCD.pcf 
par -w -intstyle ise -ol high -mt off LCD_map.ncd LCD.ncd LCD.pcf 
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml LCD.twx LCD.ncd -o LCD.twr LCD.pcf -ucf top.ucf 
bitgen -intstyle ise -f LCD.ut LCD.ncd