Release 14.2 - xst P.28xd (nt64) Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.08 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.08 secs --> Reading design: top.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Parsing 3) HDL Elaboration 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Partition Report 8) Design Summary 8.1) Primitive and Black Box Usage 8.2) Device utilization summary 8.3) Partition Resource Summary 8.4) Timing Report 8.4.1) Clock Information 8.4.2) Asynchronous Control Signals Information 8.4.3) Timing Summary 8.4.4) Timing Details 8.4.5) Cross Clock Domains Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "top.prj" Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "top" Output Format : NGC Target Device : xc6slx9-2-tqg144 ---- Source Options Top Module Name : top Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : LUT RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Shift Register Extraction : YES ROM Style : Auto Resource Sharing : YES Asynchronous To Synchronous : NO Shift Register Minimum Size : 2 Use DSP Block : Auto Automatic Register Balancing : No ---- Target Options LUT Combining : Auto Reduce Control Sets : Auto Add IO Buffers : YES Global Maximum Fanout : 100000 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Optimize Instantiated Primitives : NO Use Clock Enable : Auto Use Synchronous Set : Auto Use Synchronous Reset : Auto Pack IO Registers into IOBs : Auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Power Reduction : NO Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 DSP48 Utilization Ratio : 100 Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Parsing * ========================================================================= Analyzing Verilog file "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\SR04\hextobcd.v" into library work Parsing module . Analyzing Verilog file "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\SR04\SR04_Sensor.v" into library work Parsing module . Analyzing Verilog file "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\SR04\LCD.v" into library work Parsing module . Analyzing Verilog file "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\SR04\top.v" into library work Parsing module . ========================================================================= * HDL Elaboration * ========================================================================= WARNING:HDLCompiler:1016 - "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\SR04\top.v" Line 60: Port CLK180 is not connected to this instance Elaborating module . Elaborating module . Elaborating module . Elaborating module . WARNING:HDLCompiler:413 - "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\SR04\LCD.v" Line 135: Result of 10-bit expression is truncated to fit in 9-bit target. WARNING:HDLCompiler:413 - "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\SR04\LCD.v" Line 229: Result of 32-bit expression is truncated to fit in 1-bit target. Elaborating module . WARNING:HDLCompiler:1127 - "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\SR04\hextobcd.v" Line 41: Assignment to bcd ignored, since the identifier is never used WARNING:HDLCompiler:189 - "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\SR04\LCD.v" Line 259: Size mismatch in connection of port . Formal port size is 31-bit while actual signal size is 32-bit. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\SR04\top.v". Found 1-bit register for signal . Found 1-bit register for signal . Found 2-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 2-bit adder for signal created at line 52. Summary: inferred 1 Adder/Subtractor(s). inferred 6 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\SR04\SR04_Sensor.v". Found 32-bit register for signal . Found 1-bit register for signal . Found 32-bit register for signal . Found 4-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 1-bit register for signal . Found 4-bit register for signal . Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 11 | | Inputs | 3 | | Outputs | 5 | | Clock | clk (rising_edge) | | Power Up State | 0011 | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine for signal . ----------------------------------------------------------------------- | States | 5 | | Transitions | 10 | | Inputs | 5 | | Outputs | 5 | | Clock | clk (rising_edge) | | Power Up State | 0101 | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 32-bit adder for signal created at line 46. Found 32-bit adder for signal created at line 61. Found 32-bit adder for signal created at line 111. Found 32-bit adder for signal created at line 127. Found 32-bit comparator greater for signal created at line 55 Found 32-bit comparator greater for signal created at line 78 Found 32-bit comparator greater for signal created at line 88 Summary: inferred 4 Adder/Subtractor(s). inferred 162 D-type flip-flop(s). inferred 3 Comparator(s). inferred 7 Multiplexer(s). inferred 2 Finite State Machine(s). Unit synthesized. Synthesizing Unit . Related source file is "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\SR04\LCD.v". LCD_BLANK = 8'b00100000 LCD_DASH = 8'b00101101 LCD_COLON = 8'b00111010 LCD_PERIODE = 8'b00101110 LCD_EQUAL = 8'b00111101 LCD_0 = 8'b00110000 LCD_1 = 8'b00110001 LCD_2 = 8'b00110010 LCD_3 = 8'b00110011 LCD_4 = 8'b00110100 LCD_5 = 8'b00110101 LCD_6 = 8'b00110110 LCD_7 = 8'b00110111 LCD_8 = 8'b00111000 LCD_9 = 8'b00111001 LCD_A = 8'b01000001 LCD_B = 8'b01000010 LCD_C = 8'b01000011 LCD_D = 8'b01000100 LCD_E = 8'b01000101 LCD_F = 8'b01000110 LCD_G = 8'b01000111 LCD_H = 8'b01001000 LCD_I = 8'b01001001 LCD_J = 8'b01001010 LCD_K = 8'b01001011 LCD_L = 8'b01001100 LCD_M = 8'b01001101 LCD_N = 8'b01001110 LCD_O = 8'b01001111 LCD_P = 8'b01010000 LCD_Q = 8'b01010001 LCD_R = 8'b01010010 LCD_S = 8'b01010011 LCD_T = 8'b01010100 LCD_U = 8'b01010101 LCD_V = 8'b01010110 LCD_W = 8'b01010111 LCD_X = 8'b01011000 LCD_Y = 8'b01011001 LCD_Z = 8'b01011010 LCD_UNDER = 8'b01011111 LCD_S_a = 8'b01100001 LCD_S_b = 8'b01100010 LCD_S_c = 8'b01100011 LCD_S_d = 8'b01100100 LCD_S_e = 8'b01100101 LCD_S_f = 8'b01100110 LCD_S_g = 8'b01100111 LCD_S_h = 8'b01101000 LCD_S_i = 8'b01101001 LCD_S_j = 8'b01101010 LCD_S_k = 8'b01101011 LCD_S_l = 8'b01101100 LCD_S_m = 8'b01101101 LCD_S_n = 8'b01101110 LCD_S_o = 8'b01101111 LCD_S_p = 8'b01110000 LCD_S_q = 8'b01110001 LCD_S_r = 8'b01110010 LCD_S_s = 8'b01110011 LCD_S_t = 8'b01110100 LCD_S_u = 8'b01110101 LCD_S_v = 8'b01110110 LCD_S_w = 8'b01110111 LCD_S_x = 8'b01111000 LCD_S_y = 8'b01111001 LCD_S_z = 8'b01111010 WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 9-bit register for signal . Found 32-bit register for signal . Found 32-bit adder for signal created at line 121. Found 9-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 240. Found 7-bit adder for signal created at line 242. Found 7-bit adder for signal created at line 240. Found 7-bit adder for signal created at line 242. Found 7-bit adder for signal created at line 240. Found 7-bit adder for signal created at line 242. Found 7-bit adder for signal created at line 240. Found 7-bit adder for signal created at line 242. Found 7-bit adder for signal created at line 240. Found 7-bit adder for signal created at line 242. Found 7-bit adder for signal created at line 240. Found 7-bit adder for signal created at line 242. Found 7-bit adder for signal created at line 240. Found 7-bit adder for signal created at line 242. Found 7-bit adder for signal created at line 240. Found 7-bit adder for signal created at line 242. Found 7-bit adder for signal created at line 240. Found 7-bit adder for signal created at line 242. Found 7-bit adder for signal created at line 240. Found 7-bit adder for signal created at line 242. Found 8-bit comparator greater for signal created at line 229 Found 4-bit comparator lessequal for signal created at line 239 Found 4-bit comparator lessequal for signal created at line 239 Found 4-bit comparator lessequal for signal created at line 239 Found 4-bit comparator lessequal for signal created at line 239 Found 4-bit comparator lessequal for signal created at line 239 Found 4-bit comparator lessequal for signal created at line 239 Found 4-bit comparator lessequal for signal created at line 239 Found 4-bit comparator lessequal for signal created at line 239 Found 4-bit comparator lessequal for signal created at line 239 Found 4-bit comparator lessequal for signal created at line 239 Summary: inferred 22 Adder/Subtractor(s). inferred 41 D-type flip-flop(s). inferred 11 Comparator(s). inferred 38 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\SR04\hextobcd.v". Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 3-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Summary: inferred 252 Adder/Subtractor(s). inferred 252 Comparator(s). inferred 981 Multiplexer(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 279 2-bit adder : 1 32-bit adder : 5 4-bit adder : 252 7-bit adder : 20 9-bit adder : 1 # Registers : 14 1-bit register : 6 2-bit register : 1 32-bit register : 6 9-bit register : 1 # Comparators : 266 3-bit comparator greater : 1 32-bit comparator greater : 3 4-bit comparator greater : 251 4-bit comparator lessequal : 10 8-bit comparator greater : 1 # Multiplexers : 1026 1-bit 2-to-1 multiplexer : 980 32-bit 2-to-1 multiplexer : 7 40-bit 2-to-1 multiplexer : 1 8-bit 2-to-1 multiplexer : 37 9-bit 2-to-1 multiplexer : 1 # FSMs : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= WARNING:Xst:2677 - Node of sequential type is unconnected in block . Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . Unit synthesized (advanced). ========================================================================= Advanced HDL Synthesis Report Macro Statistics # Adders/Subtractors : 273 3-bit adder : 24 32-bit adder : 1 4-bit adder : 228 7-bit adder : 20 # Counters : 6 2-bit up counter : 1 32-bit up counter : 4 9-bit up counter : 1 # Registers : 70 Flip-Flops : 70 # Comparators : 266 3-bit comparator greater : 1 32-bit comparator greater : 3 4-bit comparator greater : 251 4-bit comparator lessequal : 10 8-bit comparator greater : 1 # Multiplexers : 1024 1-bit 2-to-1 multiplexer : 980 32-bit 2-to-1 multiplexer : 6 40-bit 2-to-1 multiplexer : 1 8-bit 2-to-1 multiplexer : 37 # FSMs : 2 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with sequential encoding. ------------------- State | Encoding ------------------- 0011 | 00 0001 | 01 0010 | 10 0000 | 11 ------------------- Analyzing FSM for best encoding. Optimizing FSM on signal with gray encoding. ------------------- State | Encoding ------------------- 0101 | 000 0001 | 001 0011 | 011 0000 | 010 0100 | 110 ------------------- Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 16. Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 143 Flip-Flops : 143 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Design Summary * ========================================================================= Top Level Output File Name : top.ngc Primitive and Black Box Usage: ------------------------------ # BELS : 948 # GND : 1 # INV : 6 # LUT1 : 58 # LUT2 : 67 # LUT3 : 22 # LUT4 : 34 # LUT5 : 85 # LUT6 : 453 # MUXCY : 112 # MUXF7 : 10 # VCC : 1 # XORCY : 99 # FlipFlops/Latches : 143 # FD : 9 # FDCE : 9 # FDE : 108 # FDR : 17 # Clock Buffers : 2 # BUFG : 2 # IO Buffers : 13 # IBUF : 1 # IBUFG : 1 # OBUF : 11 # DCMs : 1 # DCM_SP : 1 Device utilization summary: --------------------------- Selected Device : 6slx9tqg144-2 Slice Logic Utilization: Number of Slice Registers: 143 out of 11440 1% Number of Slice LUTs: 725 out of 5720 12% Number used as Logic: 725 out of 5720 12% Slice Logic Distribution: Number of LUT Flip Flop pairs used: 745 Number with an unused Flip Flop: 602 out of 745 80% Number with an unused LUT: 20 out of 745 2% Number of fully used LUT-FF pairs: 123 out of 745 16% Number of unique control sets: 11 IO Utilization: Number of IOs: 13 Number of bonded IOBs: 13 out of 102 12% Specific Feature Utilization: Number of BUFG/BUFGCTRLs: 2 out of 16 12% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= Timing Report NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ osc | DCM_SP:CLKFX | 143 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -2 Minimum period: 5.968ns (Maximum Frequency: 167.551MHz) Minimum input arrival time before clock: 2.083ns Maximum output required time after clock: 61.977ns Maximum combinational path delay: No path found Timing Details: --------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'osc' Clock period: 5.968ns (frequency: 167.551MHz) Total number of paths / destination ports: 7611 / 285 ------------------------------------------------------------------------- Delay: 5.968ns (Levels of Logic = 3) Source: Ultrasonic/reset_cnt_1 (FF) Destination: Ultrasonic/echo_trigger_cnt_30 (FF) Source Clock: osc rising Destination Clock: osc rising Data Path: Ultrasonic/reset_cnt_1 to Ultrasonic/echo_trigger_cnt_30 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDE:C->Q 2 0.525 1.181 Ultrasonic/reset_cnt_1 (Ultrasonic/reset_cnt_1) LUT6:I0->O 1 0.254 0.790 Ultrasonic/reset2_cnt[31]_GND_3_o_equal_36_o<31>2 (Ultrasonic/reset2_cnt[31]_GND_3_o_equal_36_o<31>1) LUT6:I4->O 7 0.250 0.910 Ultrasonic/reset2_cnt[31]_GND_3_o_equal_36_o<31>3 (Ultrasonic/reset2_cnt[31]_GND_3_o_equal_36_o) LUT6:I5->O 31 0.254 1.502 Ultrasonic/_n0250_inv1 (Ultrasonic/_n0250_inv) FDE:CE 0.302 Ultrasonic/echo_trigger_cnt_0 ---------------------------------------- Total 5.968ns (1.585ns logic, 4.383ns route) (26.6% logic, 73.4% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'osc' Total number of paths / destination ports: 1 / 1 ------------------------------------------------------------------------- Offset: 2.083ns (Levels of Logic = 1) Source: UltraSonic_InPulse (PAD) Destination: UltraSonic_InPulse_r (FF) Destination Clock: osc rising Data Path: UltraSonic_InPulse to UltraSonic_InPulse_r Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 1 1.328 0.681 UltraSonic_InPulse_IBUF (UltraSonic_InPulse_IBUF) FD:D 0.074 UltraSonic_InPulse_r ---------------------------------------- Total 2.083ns (1.402ns logic, 0.681ns route) (67.3% logic, 32.7% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'osc' Total number of paths / destination ports: 11988316228721708 / 11 ------------------------------------------------------------------------- Offset: 61.977ns (Levels of Logic = 42) Source: Ultrasonic/echo_cnt_29 (FF) Destination: lcd_data<6> (PAD) Source Clock: osc rising Data Path: Ultrasonic/echo_cnt_29 to lcd_data<6> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDE:C->Q 7 0.525 1.340 Ultrasonic/echo_cnt_29 (Ultrasonic/echo_cnt_29) LUT5:I0->O 3 0.254 1.221 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_215_o111 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_56_OUT_lut<3>) LUT6:I0->O 9 0.254 1.204 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_251_o11 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_76_OUT_cy<0>) LUT6:I3->O 15 0.235 1.383 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_291_o12 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_96_OUT_cy<0>) LUT5:I2->O 4 0.235 1.234 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_291_o111 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_94_OUT_lut<3>) LUT5:I0->O 3 0.254 1.221 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_327_o111 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_112_OUT_lut<3>) LUT6:I0->O 12 0.254 1.297 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_363_o11 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_132_OUT_cy<0>) LUT4:I1->O 7 0.235 1.138 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_403_o11 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_152_OUT_cy<0>) LUT5:I2->O 2 0.235 1.002 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_403_o111 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_150_OUT_lut<3>) LUT5:I1->O 3 0.254 1.221 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_439_o111 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_168_OUT_lut<3>) LUT6:I0->O 9 0.254 1.204 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_475_o11 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_188_OUT_cy<0>) LUT6:I3->O 15 0.235 1.383 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_515_o12 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_208_OUT_cy<0>) LUT5:I2->O 4 0.235 1.234 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_515_o111 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_206_OUT_lut<3>) LUT5:I0->O 3 0.254 1.221 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_551_o111 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_224_OUT_lut<3>) LUT6:I0->O 12 0.254 1.297 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_587_o11 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_244_OUT_cy<0>) LUT4:I1->O 7 0.235 1.138 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_627_o11 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_264_OUT_cy<0>) LUT5:I2->O 2 0.235 1.002 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_627_o111 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_262_OUT_lut<3>) LUT5:I1->O 3 0.254 1.221 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_663_o111 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_280_OUT_lut<3>) LUT6:I0->O 9 0.254 1.204 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_699_o11 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_300_OUT_cy<0>) LUT6:I3->O 15 0.235 1.383 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_739_o12 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_320_OUT_cy<0>) LUT5:I2->O 4 0.235 1.234 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_739_o111 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_318_OUT_lut<3>) LUT5:I0->O 3 0.254 1.221 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_775_o111 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_336_OUT_lut<3>) LUT6:I0->O 12 0.254 1.297 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_811_o11 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_356_OUT_cy<0>) LUT4:I1->O 7 0.235 1.138 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_851_o11 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_376_OUT_cy<0>) LUT5:I2->O 2 0.235 1.002 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_851_o111 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_374_OUT_lut<3>) LUT5:I1->O 3 0.254 1.221 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_887_o111 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_392_OUT_lut<3>) LUT6:I0->O 9 0.254 1.204 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_923_o11 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_412_OUT_cy<0>) LUT6:I3->O 16 0.235 1.410 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_963_o12 (TLCD/hextobcd0/Madd_n1705_Madd_cy<0>) LUT5:I2->O 4 0.235 1.234 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_963_o111 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_430_OUT_lut<3>) LUT5:I0->O 3 0.254 1.221 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_1000_o11 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_448_OUT_lut<3>) LUT6:I0->O 14 0.254 1.355 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_1035_o11 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_468_OUT_cy<0>) LUT4:I1->O 9 0.235 1.204 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_1076_o131 (TLCD/bcd1<38>) LUT5:I2->O 2 0.235 1.002 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_1076_o11 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_486_OUT_lut<3>) LUT5:I1->O 4 0.254 1.259 TLCD/hextobcd0/Mmux_GND_5_o_GND_5_o_MUX_1112_o11 (TLCD/hextobcd0/Madd_GND_5_o_GND_5_o_add_504_OUT_lut<3>) LUT6:I0->O 3 0.254 0.766 TLCD/hextobcd0/Mmux_result<33>131 (TLCD/Madd_n0203[6:0]_cy<0>) LUT6:I5->O 2 0.254 0.726 TLCD/Madd_n0203[6:0]_cy<1>11 (TLCD/Madd_n0203[6:0]_cy<1>) LUT6:I5->O 2 0.254 0.834 TLCD/Madd_n0203[6:0]_cy<3>11 (TLCD/Madd_n0203[6:0]_cy<3>) LUT6:I4->O 1 0.250 0.910 TLCD/Mmux_lcd_db429 (TLCD/Mmux_lcd_db428) LUT6:I3->O 1 0.235 0.910 TLCD/Mmux_lcd_db4210 (TLCD/Mmux_lcd_db429) LUT6:I3->O 1 0.235 1.137 TLCD/Mmux_lcd_db4211 (TLCD/Mmux_lcd_db4210) LUT6:I0->O 1 0.254 0.958 TLCD/Mmux_lcd_db4212_SW0 (N19) LUT6:I2->O 1 0.254 0.681 TLCD/Mmux_lcd_db4212 (lcd_data_6_OBUF) OBUF:I->O 2.912 lcd_data_6_OBUF (lcd_data<6>) ---------------------------------------- Total 61.977ns (13.505ns logic, 48.472ns route) (21.8% logic, 78.2% route) ========================================================================= Cross Clock Domains Report: -------------------------- Clock to Setup on destination clock osc ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ osc | 5.968| | | | ---------------+---------+---------+---------+---------+ ========================================================================= Total REAL time to Xst completion: 16.00 secs Total CPU time to Xst completion: 15.28 secs --> Total memory usage is 275084 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 62 ( 0 filtered) Number of infos : 16 ( 0 filtered)