xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/SR04/top.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/SR04/top.syr" 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/SR04/top.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/SR04/top.syr" 
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Ucf.ucf -p xc6slx9-tqg144-2 top.ngc top.ngd  
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Ucf.ucf -p xc6slx9-tqg144-2 top.ngc top.ngd  
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Ucf.ucf -p xc6slx9-tqg144-2 top.ngc top.ngd  
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/SR04/top.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/SR04/top.syr" 
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Ucf.ucf -p xc6slx9-tqg144-2 top.ngc top.ngd  
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Ucf.ucf -p xc6slx9-tqg144-2 top.ngc top.ngd  
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/SR04/top.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/SR04/top.syr" 
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Ucf.ucf -p xc6slx9-tqg144-2 top.ngc top.ngd  
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o top_map.ncd top.ngd top.pcf 
par -w -intstyle ise -ol high -mt off top_map.ncd top.ncd top.pcf 
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf Ucf.ucf 
bitgen -intstyle ise -f top.ut top.ncd 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/SR04/top.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/SR04/top.syr" 
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Ucf.ucf -p xc6slx9-tqg144-2 top.ngc top.ngd  
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o top_map.ncd top.ngd top.pcf 
par -w -intstyle ise -ol high -mt off top_map.ncd top.ncd top.pcf 
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf Ucf.ucf 
bitgen -intstyle ise -f top.ut top.ncd 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/SR04/top.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/SR04/top.syr" 
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Ucf.ucf -p xc6slx9-tqg144-2 top.ngc top.ngd  
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o top_map.ncd top.ngd top.pcf 
par -w -intstyle ise -ol high -mt off top_map.ncd top.ncd top.pcf 
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf Ucf.ucf 
bitgen -intstyle ise -f top.ut top.ncd