Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.2 (WebPack) - P.28xd Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx9
Project ID (random number) ea081235f4e2469da4cf3e33d5a71d61.B30D3935F43C448D9069F55B4C16A3B4.4 Target Package: tqg144
Registration ID __0_0_0 Target Speed: -2
Date Generated 2015-02-04T17:57:00 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i5-4670 CPU @ 3.40GHz CPU Speed 3392 MHz
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i5-4670 CPU @ 3.40GHz CPU Speed 3392 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=3
  • 2-bit up counter=1
  • 28-bit up counter=1
  • 32-bit up counter=1
 FSMs=1 Multiplexers=1
  • 1-bit 2-to-1 multiplexer=1
 Registers=3
  • Flip-Flops=3
 		MiscellaneousStatistics
  • AGG_BONDED_IO=2
  • AGG_IO=2
  • AGG_LOCED_IO=2
  • AGG_SLICE=43
  • NUM_BONDED_IOB=2
  • NUM_BSFULL=66
  • NUM_BSLUTONLY=81
  • NUM_BSUSED=147
  • NUM_BUFG=1
  • NUM_LOCED_IOB=2
  • NUM_LOGIC_O5ANDO6=2
  • NUM_LOGIC_O5ONLY=56
  • NUM_LOGIC_O6ONLY=87
  • NUM_LUT_RT_DRIVES_CARRY4=2
  • NUM_LUT_RT_EXO6=2
  • NUM_LUT_RT_O6=56
  • NUM_SLICEL=16
  • NUM_SLICEX=27
  • NUM_SLICE_CARRY4=15
  • NUM_SLICE_CONTROLSET=4
  • NUM_SLICE_CYINIT=207
  • NUM_SLICE_F7MUX=1
  • NUM_SLICE_FF=66
  • NUM_SLICE_UNUSEDCTRL=22
  • NUM_UNUSABLE_FF_BELS=22
 		NetStatistics
  • NumNets_Active=164
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=3
  • NumNodesOfType_Active_BOUNCEIN=16
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=4
  • NumNodesOfType_Active_CLKPIN=21
  • NumNodesOfType_Active_CLKPINFEED=6
  • NumNodesOfType_Active_CNTRLPIN=21
  • NumNodesOfType_Active_DOUBLE=74
  • NumNodesOfType_Active_GENERIC=2
  • NumNodesOfType_Active_GLOBAL=20
  • NumNodesOfType_Active_INPUT=14
  • NumNodesOfType_Active_IOBIN2OUT=1
  • NumNodesOfType_Active_IOBOUTPUT=1
  • NumNodesOfType_Active_LUTINPUT=309
  • NumNodesOfType_Active_OUTBOUND=151
  • NumNodesOfType_Active_OUTPUT=169
  • NumNodesOfType_Active_PADINPUT=1
  • NumNodesOfType_Active_PADOUTPUT=1
  • NumNodesOfType_Active_PINBOUNCE=40
  • NumNodesOfType_Active_PINFEED=352
  • NumNodesOfType_Active_QUAD=13
  • NumNodesOfType_Active_REGINPUT=1
  • NumNodesOfType_Active_SINGLE=161
  • NumNodesOfType_Vcc_HVCCOUT=15
  • NumNodesOfType_Vcc_KVCCOUT=1
  • NumNodesOfType_Vcc_LUTINPUT=58
  • NumNodesOfType_Vcc_PINBOUNCE=1
  • NumNodesOfType_Vcc_PINFEED=58
  • NumNodesOfType_Vcc_REGINPUT=1
 SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBS=2
  • SLICEL-SLICEM=8
  • SLICEX-SLICEL=3
  • SLICEX-SLICEM=6
 		SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • CARRY4=15
  • HARD0=2
  • IOB=2
  • IOB_IMUX=1
  • IOB_INBUF=1
  • IOB_OUTBUF=1
  • LUT5=58
  • LUT6=147
  • PAD=2
  • REG_SR=66
  • SELMUX2_1=1
  • SLICEL=16
  • SLICEX=27
 
Configuration Data
IOB_OUTBUF
  • DRIVEATTRBOX=[12:1]
  • SLEW=[SLOW:1]
  • SUSPEND=[3STATE:1]
 REG_SR
  • CK=[CK:66] [CK_INV:0]
  • LATCH_OR_FF=[FF:66]
  • SRINIT=[SRINIT0:65] [SRINIT1:1]
  • SYNC_ATTR=[ASYNC:64] [SYNC:2]
 SLICEL
  • CLK=[CLK:1] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:20] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
 BUFG_BUFG
  • I0=1
  • O=1
 CARRY4
  • CIN=13
  • CO3=13
  • CYINIT=2
  • DI0=15
  • DI1=15
  • DI2=15
  • DI3=13
  • O0=15
  • O1=15
  • O2=15
  • O3=15
  • S0=15
  • S1=15
  • S2=15
  • S3=15
 HARD0
  • 0=2
 IOB
  • I=1
  • O=1
  • PAD=2
 IOB_IMUX
  • I=1
  • OUT=1
 IOB_INBUF
  • OUT=1
  • PAD=1
 IOB_OUTBUF
  • IN=1
  • OUT=1
 LUT5
  • O5=58
 LUT6
  • A1=17
  • A2=17
  • A3=19
  • A4=27
  • A5=142
  • A6=145
  • O6=147
 PAD
  • PAD=2
 REG_SR
  • CE=3
  • CK=66
  • D=66
  • Q=66
  • SR=63
 SELMUX2_1
  • 0=1
  • 1=1
  • OUT=1
  • S0=1
 SLICEL
  • A=1
  • A3=1
  • A4=1
  • A5=16
  • A6=16
  • AMUX=15
  • AQ=1
  • AX=1
  • B=1
  • B1=1
  • B2=1
  • B3=1
  • B4=1
  • B5=16
  • B6=16
  • BMUX=15
  • C1=1
  • C2=1
  • C3=1
  • C4=1
  • C5=16
  • C6=16
  • CIN=13
  • CLK=1
  • CMUX=15
  • COUT=13
  • CQ=1
  • CX=1
  • D1=1
  • D2=1
  • D3=1
  • D4=1
  • D5=14
  • D6=16
  • DMUX=15
  • SR=1
 SLICEX
  • A=10
  • A1=7
  • A2=7
  • A3=8
  • A4=11
  • A5=25
  • A6=25
  • AQ=16
  • B=4
  • B1=4
  • B2=4
  • B3=4
  • B4=5
  • B5=20
  • B6=21
  • BQ=17
  • C=3
  • C1=2
  • C2=2
  • C3=2
  • C4=4
  • C5=17
  • C6=17
  • CE=2
  • CLK=20
  • CQ=15
  • D=2
  • D1=1
  • D2=1
  • D3=1
  • D4=3
  • D5=18
  • D6=18
  • DQ=16
  • SR=18
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
Start 0 0 0 0 0 0 0
_impact 42 26 0 0 0 0 0
bitgen 389 386 0 0 0 0 0
edif2ngd 1 1 0 0 0 0 0
map 479 394 0 0 0 0 0
netgen 9 9 0 0 0 0 0
ngc2edif 2 2 0 0 0 0 0
ngcbuild 9 9 0 0 0 0 0
ngdbuild 509 503 0 0 0 0 0
obngc 9 9 0 0 0 0 0
par 391 390 0 0 0 0 0
trce 375 375 0 0 0 0 0
xst 807 750 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Constraints Editor PROP_intProjectCreationTimestamp=2015-02-04T17:46:09
PROP_intWbtProjectID=B30D3935F43C448D9069F55B4C16A3B4 PROP_intWbtProjectIteration=4
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_AutoTop=true
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx9
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=tqg144
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-2
PROP_PreferredLanguage=Verilog FILE_UCF=1
FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=1 NGDBUILD_NUM_FDC=60 NGDBUILD_NUM_FDCE=1
NGDBUILD_NUM_FDE=2 NGDBUILD_NUM_FDR=2 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_INV=4
NGDBUILD_NUM_LUT1=58 NGDBUILD_NUM_LUT2=61 NGDBUILD_NUM_LUT3=5 NGDBUILD_NUM_LUT4=2
NGDBUILD_NUM_LUT6=17 NGDBUILD_NUM_MUXCY=58 NGDBUILD_NUM_MUXF7=1 NGDBUILD_NUM_OBUF=1
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=60
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=1 NGDBUILD_NUM_FDC=60 NGDBUILD_NUM_FDCE=1
NGDBUILD_NUM_FDE=2 NGDBUILD_NUM_FDR=2 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=4 NGDBUILD_NUM_LUT1=58 NGDBUILD_NUM_LUT2=61 NGDBUILD_NUM_LUT3=5
NGDBUILD_NUM_LUT4=2 NGDBUILD_NUM_LUT6=17 NGDBUILD_NUM_MUXCY=58 NGDBUILD_NUM_MUXF7=1
NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=60
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx9-2-tqg144
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5