`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:46:28 02/04/2015 
// Design Name: 
// Module Name:    top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module top(
	input clk,
	output reg SERVOMotor_PWM_SIG
    );

reg [31:0] cnt = 0;
reg [27:0] cnt_time = 0;
reg toggle = 0;
wire stop_flag;
wire ontime_tick;
reg offtime_tick;
reg [1:0]reset_cnt = 0;
reg reset = 1'b1;
parameter S0 = 0, S1 = 1, S2 = 2;
always@(posedge clk)
begin
	if(reset==1'b1)
	begin
	reset_cnt <= reset_cnt + 1'b1;
	end 
   if(reset_cnt==2)
	begin
	reset <= 1'b0;
	end
end 
always@(posedge clk or posedge reset)
begin
	if(reset == 1'b1)
	begin
		cnt_time <= 32'd0;
		toggle <= 1'b0;
	end
	else if(cnt_time == 28'd250000000) //20ms 
	begin
		cnt_time <= 28'd0;
		toggle <= ~toggle;
	end 
	else cnt_time <= cnt_time + 1'b1;
end 


always@(posedge clk or posedge reset)
begin
	if(reset == 1'b1)
	begin
		cnt <= 32'd0;
	end
	else if(cnt == 32'd1000000) //20ms 
	begin
		cnt <= 32'd0;
	end 
	else cnt <= cnt + 1'b1;
end 

assign ontime_tick = (cnt == 32'd0)? 1'b1:1'b0;
//assign offtime_tick = (cnt == 32'd100000)? 1'b1:1'b0;
always@(*)
begin
	case(toggle)
	0:
	begin
		if(cnt == 32'd115000) //2.3ms
		begin
			offtime_tick = 1;
		end 
		else offtime_tick = 0;
	end
	1:
	begin
		if(cnt == 32'd32500)//0.65ms
		begin
			offtime_tick = 1;
		end 
		else offtime_tick = 0;
	end
	default offtime_tick = 0;
	endcase

end 

reg [2:0]state=0;
always@(posedge clk)
begin
if(reset)
begin
	SERVOMotor_PWM_SIG <= 1'b0;
	state <= 3'd0;
end
else 
begin
	case(state)
	S0:begin
			 SERVOMotor_PWM_SIG <= 1'b0;
			 state <= S1;
	end 
	S1:
	begin 
			if(ontime_tick)
			begin
				SERVOMotor_PWM_SIG <= 1'b1;
				state <= S2;
			end 
	end 
	S2: begin
			if(offtime_tick)
			begin
				SERVOMotor_PWM_SIG <= 1'b0;
				state <= S1;
			end 
	end 
	endcase
end 
end 

endmodule