]> Release 14.2 Trace (nt64)Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf Ucf.ucf top.ncdtop.ncdtop.pcftop.pcfxc6slx9C-2PRODUCTION 1.22 2012-07-0913INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.TS_osc = PERIOD TIMEGRP "tnm_osc" 20 ns HIGH 50%;80000708.000Paths for end point reset_cnt_1 (SLICE_X8Y25.BX), 2 paths 17.725reset_cnt_1reset_cnt_12.2400.00020.0000.035reset_cnt_1reset_cnt_11SLICE_X8Y25.CLKosc_IBUFGSLICE_X8Y25.BQTcko0.525reset_cnt<1>reset_cnt_1SLICE_X8Y26.A2net10.699reset_cnt<1>SLICE_X8Y26.ATilo0.254Result<1>Mcount_reset_cnt_xor<1>11SLICE_X8Y25.BXnet10.677Result<1>SLICE_X8Y25.CLKTdick0.085reset_cnt<1>reset_cnt_10.8641.3762.240osc_IBUFG38.661.417.921reset_cnt_0reset_cnt_12.0440.00020.0000.035reset_cnt_0reset_cnt_11SLICE_X8Y25.CLKosc_IBUFGSLICE_X8Y25.AQTcko0.525reset_cnt<1>reset_cnt_0SLICE_X8Y26.A4net20.503reset_cnt<0>SLICE_X8Y26.ATilo0.254Result<1>Mcount_reset_cnt_xor<1>11SLICE_X8Y25.BXnet10.677Result<1>SLICE_X8Y25.CLKTdick0.085reset_cnt<1>reset_cnt_10.8641.1802.044osc_IBUFG42.357.7Paths for end point reset_cnt_0 (SLICE_X8Y25.CE), 1 path 18.293resetreset_cnt_01.2510.42120.0000.035resetreset_cnt_00SLICE_X8Y26.CLKosc_IBUFGSLICE_X8Y26.AMUXTshcko0.576Result<1>resetSLICE_X8Y25.CEnet50.362resetSLICE_X8Y25.CLKTceck0.313reset_cnt<1>reset_cnt_00.8890.3621.251osc_IBUFG71.128.9Paths for end point reset_cnt_1 (SLICE_X8Y25.CE), 1 path 18.353resetreset_cnt_11.1910.42120.0000.035resetreset_cnt_10SLICE_X8Y26.CLKosc_IBUFGSLICE_X8Y26.AMUXTshcko0.576Result<1>resetSLICE_X8Y25.CEnet50.362resetSLICE_X8Y25.CLKTceck0.253reset_cnt<1>reset_cnt_10.8290.3621.191osc_IBUFG69.630.4Hold Paths: TS_osc = PERIOD TIMEGRP "tnm_osc" 20 ns HIGH 50%; Paths for end point reset (SLICE_X8Y26.A4), 1 path 0.316reset_cnt_0reset0.576-0.2600.0000.000reset_cnt_0reset1SLICE_X8Y25.CLKosc_IBUFGSLICE_X8Y25.AQTcko0.234reset_cnt<1>reset_cnt_0SLICE_X8Y26.A4net20.211reset_cnt<0>SLICE_X8Y26.CLKTah0.131Result<1>reset_glue_rstreset0.3650.2110.576osc_IBUFG63.436.6Paths for end point reset (SLICE_X8Y26.A2), 1 path 0.444reset_cnt_1reset0.704-0.2600.0000.000reset_cnt_1reset1SLICE_X8Y25.CLKosc_IBUFGSLICE_X8Y25.BQTcko0.234reset_cnt<1>reset_cnt_1SLICE_X8Y26.A2net10.339reset_cnt<1>SLICE_X8Y26.CLKTah0.131Result<1>reset_glue_rstreset0.3650.3390.704osc_IBUFG51.848.2Paths for end point reset_cnt_0 (SLICE_X8Y25.A6), 1 path 0.455reset_cnt_0reset_cnt_00.4550.0000.0000.000reset_cnt_0reset_cnt_01SLICE_X8Y25.CLKosc_IBUFGSLICE_X8Y25.AQTcko0.234reset_cnt<1>reset_cnt_0SLICE_X8Y25.A6net20.024reset_cnt<0>SLICE_X8Y25.CLKTah0.197reset_cnt<1>Mcount_reset_cnt_xor<0>11_INV_0reset_cnt_00.4310.0240.455osc_IBUFG94.75.3Component Switching Limit Checks: TS_osc = PERIOD TIMEGRP "tnm_osc" 20 ns HIGH 50%;TS_clk_main = PERIOD TIMEGRP "clk_main" TS_osc HIGH 50%;127200000104608.758Paths for end point TLCD/lcd_cnt_8 (SLICE_X6Y58.SR), 1 path 11.242resetTLCD/lcd_cnt_83.6754.59820.0000.485resetTLCD/lcd_cnt_80SLICE_X8Y26.CLKosc_IBUFGSLICE_X8Y26.AMUXTshcko0.576Result<1>resetSLICE_X6Y58.SRnet52.877resetSLICE_X6Y58.CLKTrck0.222TLCD/lcd_cnt<8>TLCD/lcd_cnt_80.7982.8773.675clk_main_BUFG21.778.3Paths for end point TLCD/lcd_cnt_5 (SLICE_X6Y57.SR), 1 path 11.258resetTLCD/lcd_cnt_53.6574.60020.0000.485resetTLCD/lcd_cnt_50SLICE_X8Y26.CLKosc_IBUFGSLICE_X8Y26.AMUXTshcko0.576Result<1>resetSLICE_X6Y57.SRnet52.848resetSLICE_X6Y57.CLKTrck0.233TLCD/lcd_cnt<7>TLCD/lcd_cnt_50.8092.8483.657clk_main_BUFG22.177.9Paths for end point TLCD/lcd_cnt_4 (SLICE_X6Y57.SR), 1 path 11.269resetTLCD/lcd_cnt_43.6464.60020.0000.485resetTLCD/lcd_cnt_40SLICE_X8Y26.CLKosc_IBUFGSLICE_X8Y26.AMUXTshcko0.576Result<1>resetSLICE_X6Y57.SRnet52.848resetSLICE_X6Y57.CLKTrck0.222TLCD/lcd_cnt<7>TLCD/lcd_cnt_40.7982.8483.646clk_main_BUFG21.978.1Hold Paths: TS_clk_main = PERIOD TIMEGRP "clk_main" TS_osc HIGH 50%; Paths for end point RTC1307/stop_state (SLICE_X22Y39.A6), 1 path 0.417RTC1307/stop_stateRTC1307/stop_state0.4170.0000.0000.000RTC1307/stop_stateRTC1307/stop_state1SLICE_X22Y39.CLKclk_main_BUFGSLICE_X22Y39.AQTcko0.200RTC1307/clk_state_FSM_FFd4RTC1307/stop_stateSLICE_X22Y39.A6net50.027RTC1307/stop_stateSLICE_X22Y39.CLKTah0.190RTC1307/clk_state_FSM_FFd4RTC1307/clk_state_clk_state[7]_stop_state_Select_110_oRTC1307/stop_state0.3900.0270.417clk_main_BUFG93.56.5Paths for end point RTC1307/cnt_send_2 (SLICE_X6Y48.D6), 1 path 0.418RTC1307/cnt_send_2RTC1307/cnt_send_20.4180.0000.0000.000RTC1307/cnt_send_2RTC1307/cnt_send_21SLICE_X6Y48.CLKclk_main_BUFGSLICE_X6Y48.DQTcko0.200RTC1307/cnt_send<2>RTC1307/cnt_send_2SLICE_X6Y48.D6net80.028RTC1307/cnt_send<2>SLICE_X6Y48.CLKTah0.190RTC1307/cnt_send<2>RTC1307/cnt_send_2_rstpotRTC1307/cnt_send_20.3900.0280.418clk_main_BUFG93.36.7Paths for end point RTC1307/cnt_send_0 (SLICE_X6Y48.A6), 1 path 0.427RTC1307/cnt_send_0RTC1307/cnt_send_00.4270.0000.0000.000RTC1307/cnt_send_0RTC1307/cnt_send_01SLICE_X6Y48.CLKclk_main_BUFGSLICE_X6Y48.AQTcko0.200RTC1307/cnt_send<2>RTC1307/cnt_send_0SLICE_X6Y48.A6net90.037RTC1307/cnt_send<0>SLICE_X6Y48.CLKTah0.190RTC1307/cnt_send<2>RTC1307/cnt_send_0_rstpotRTC1307/cnt_send_00.3900.0370.427clk_main_BUFG91.38.7Component Switching Limit Checks: TS_clk_main = PERIOD TIMEGRP "clk_main" TS_osc HIGH 50%;0oscosc8.758000012728021128.758114.181Thu Feb 12 17:18:41 2015 TraceTrace Settings Peak Memory Usage: 240 MB