`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:01:48 12/18/2014
// Design Name:   I2C
// Module Name:   H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/LED/TEST/i2c_testbench.v
// Project Name:  TEST
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: I2C
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module i2c_testbench;

	// Inputs
	reg clk;
	reg reset;
	reg [7:0]scl_length = 0;
	// Outputs
	wire scl;
	wire [7:0] hour;
	wire [7:0] minute;
	wire [7:0] sec;
	reg [7:0]reset_start_length = 0;
	wire reset_start;
	wire reset_state_w;
	// Bidirs
	wire sda;


	// Instantiate the Unit Under Test (UUT)
	I2C uut (
		.clk(clk), 
		.reset(reset), 
		.scl(scl), 
		.sda(sda), 
		.hour(hour), 
		.minute(minute), 
		.sec(sec),
		.reset_start(reset_start),
		.reset_state_w(reset_state_w)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;
		scl_length = 0;
		reset_start_length = 0;
		// Wait 100 ns for global reset to finish
		#100;
      reset = 1;  
		// Add stimulus here

	end
   always
	begin
		#10 clk = ~clk;
	end
	always@(posedge scl or posedge reset_start)
	begin
		if(reset_start)
		begin
		scl_length <= 8'd1;
		end
		else scl_length <= scl_length + 1'b1;
	end 
	
	always@(posedge reset_state_w)
	begin
		 reset_start_length <=reset_start_length + 1'b1;
	end 
//	
//	wire tick_max = (scl_length >8'd28)? 1'b1: 1'b0;
//	wire ack = (scl_length == 8'd9||scl_length == 8'd10||scl_length == 8'd18||scl_length == 8'd19||scl_length == 8'd27||scl_length == 8'd28)? 1'b0: 1'bz;	
//	wire ack = (scl_length == 8'd10||scl_length == 8'd19||scl_length == 8'd28||scl_length == 8'd38||scl_length == 8'd47||scl_length == 8'd56)? 1'b0: 1'bz;	
//	wire tick = (scl_length == 8'd58||scl_length == 8'd59||scl_length == 8'd60||scl_length == 8'd61)? 1'b1: 1'b0;	
//	wire tick = (scl_length == 8'd15||scl_length == 8'd17)? 1'b1: 1'b0;	
	wire ack = (scl_length == 8'd10||scl_length == 8'd19||scl_length == 8'd28)? 1'b0: 1'bz;	
	assign sda = ack;
//	assign sda = ack|tick;
//	assign sda = (reset_start_length >8'd10)?1'bz : ack;
endmodule