]> Release 14.2 Trace (nt64)Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf top.ucf top.ncdtop.ncdtop.pcftop.pcfxc6slx9C-2PRODUCTION 1.22 2012-07-0913INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.TS_osc = PERIOD TIMEGRP "tnm_osc" 20 ns HIGH 50%;00000008.000Component Switching Limit Checks: TS_osc = PERIOD TIMEGRP "tnm_osc" 20 ns HIGH 50%;TS_clk_main = PERIOD TIMEGRP "clk_main" TS_osc HIGH 50%;7118000082305.834Paths for end point timer_cnt_15 (SLICE_X14Y43.B3), 36 paths 14.166tx_clk_count_8timer_cnt_155.4890.01020.0000.335tx_clk_count_8timer_cnt_154SLICE_X17Y40.CLKclk_main_BUFGSLICE_X17Y40.DQTcko0.430tx_clk_count<8>tx_clk_count_8SLICE_X17Y41.D2net30.934tx_clk_count<8>SLICE_X17Y41.DTilo0.259tx_clk_count<11>GND_1_o_GND_1_o_equal_10_o<11>2SLICE_X12Y39.A3net160.984GND_1_o_GND_1_o_equal_10_o<11>1SLICE_X12Y39.ATilo0.254tx_clk_count<0>GND_1_o_GND_1_o_equal_10_o<11>3SLICE_X15Y37.D3net90.878GND_1_o_GND_1_o_equal_10_oSLICE_X15Y37.DTilo0.259timer_cnt<2>_n0419_inv1SLICE_X14Y43.B3net121.142_n0419_invSLICE_X14Y43.CLKTas0.349timer_cnt<17>timer_cnt_15_rstpottimer_cnt_151.5513.9385.489clk_main_BUFG28.371.714.368tx_clk_count_7timer_cnt_155.2870.01020.0000.335tx_clk_count_7timer_cnt_154SLICE_X17Y40.CLKclk_main_BUFGSLICE_X17Y40.CQTcko0.430tx_clk_count<8>tx_clk_count_7SLICE_X17Y41.D1net30.732tx_clk_count<7>SLICE_X17Y41.DTilo0.259tx_clk_count<11>GND_1_o_GND_1_o_equal_10_o<11>2SLICE_X12Y39.A3net160.984GND_1_o_GND_1_o_equal_10_o<11>1SLICE_X12Y39.ATilo0.254tx_clk_count<0>GND_1_o_GND_1_o_equal_10_o<11>3SLICE_X15Y37.D3net90.878GND_1_o_GND_1_o_equal_10_oSLICE_X15Y37.DTilo0.259timer_cnt<2>_n0419_inv1SLICE_X14Y43.B3net121.142_n0419_invSLICE_X14Y43.CLKTas0.349timer_cnt<17>timer_cnt_15_rstpottimer_cnt_151.5513.7365.287clk_main_BUFG29.370.714.452tx_clk_count_1timer_cnt_155.2030.01020.0000.335tx_clk_count_1timer_cnt_154SLICE_X17Y39.CLKclk_main_BUFGSLICE_X17Y39.AQTcko0.430tx_clk_count<4>tx_clk_count_1SLICE_X17Y41.D3net30.648tx_clk_count<1>SLICE_X17Y41.DTilo0.259tx_clk_count<11>GND_1_o_GND_1_o_equal_10_o<11>2SLICE_X12Y39.A3net160.984GND_1_o_GND_1_o_equal_10_o<11>1SLICE_X12Y39.ATilo0.254tx_clk_count<0>GND_1_o_GND_1_o_equal_10_o<11>3SLICE_X15Y37.D3net90.878GND_1_o_GND_1_o_equal_10_oSLICE_X15Y37.DTilo0.259timer_cnt<2>_n0419_inv1SLICE_X14Y43.B3net121.142_n0419_invSLICE_X14Y43.CLKTas0.349timer_cnt<17>timer_cnt_15_rstpottimer_cnt_151.5513.6525.203clk_main_BUFG29.870.2Paths for end point timer_cnt_14 (SLICE_X14Y43.A4), 36 paths 14.281tx_clk_count_8timer_cnt_145.3740.01020.0000.335tx_clk_count_8timer_cnt_144SLICE_X17Y40.CLKclk_main_BUFGSLICE_X17Y40.DQTcko0.430tx_clk_count<8>tx_clk_count_8SLICE_X17Y41.D2net30.934tx_clk_count<8>SLICE_X17Y41.DTilo0.259tx_clk_count<11>GND_1_o_GND_1_o_equal_10_o<11>2SLICE_X12Y39.A3net160.984GND_1_o_GND_1_o_equal_10_o<11>1SLICE_X12Y39.ATilo0.254tx_clk_count<0>GND_1_o_GND_1_o_equal_10_o<11>3SLICE_X15Y37.D3net90.878GND_1_o_GND_1_o_equal_10_oSLICE_X15Y37.DTilo0.259timer_cnt<2>_n0419_inv1SLICE_X14Y43.A4net121.027_n0419_invSLICE_X14Y43.CLKTas0.349timer_cnt<17>timer_cnt_14_rstpottimer_cnt_141.5513.8235.374clk_main_BUFG28.971.114.483tx_clk_count_7timer_cnt_145.1720.01020.0000.335tx_clk_count_7timer_cnt_144SLICE_X17Y40.CLKclk_main_BUFGSLICE_X17Y40.CQTcko0.430tx_clk_count<8>tx_clk_count_7SLICE_X17Y41.D1net30.732tx_clk_count<7>SLICE_X17Y41.DTilo0.259tx_clk_count<11>GND_1_o_GND_1_o_equal_10_o<11>2SLICE_X12Y39.A3net160.984GND_1_o_GND_1_o_equal_10_o<11>1SLICE_X12Y39.ATilo0.254tx_clk_count<0>GND_1_o_GND_1_o_equal_10_o<11>3SLICE_X15Y37.D3net90.878GND_1_o_GND_1_o_equal_10_oSLICE_X15Y37.DTilo0.259timer_cnt<2>_n0419_inv1SLICE_X14Y43.A4net121.027_n0419_invSLICE_X14Y43.CLKTas0.349timer_cnt<17>timer_cnt_14_rstpottimer_cnt_141.5513.6215.172clk_main_BUFG30.070.014.567tx_clk_count_1timer_cnt_145.0880.01020.0000.335tx_clk_count_1timer_cnt_144SLICE_X17Y39.CLKclk_main_BUFGSLICE_X17Y39.AQTcko0.430tx_clk_count<4>tx_clk_count_1SLICE_X17Y41.D3net30.648tx_clk_count<1>SLICE_X17Y41.DTilo0.259tx_clk_count<11>GND_1_o_GND_1_o_equal_10_o<11>2SLICE_X12Y39.A3net160.984GND_1_o_GND_1_o_equal_10_o<11>1SLICE_X12Y39.ATilo0.254tx_clk_count<0>GND_1_o_GND_1_o_equal_10_o<11>3SLICE_X15Y37.D3net90.878GND_1_o_GND_1_o_equal_10_oSLICE_X15Y37.DTilo0.259timer_cnt<2>_n0419_inv1SLICE_X14Y43.A4net121.027_n0419_invSLICE_X14Y43.CLKTas0.349timer_cnt<17>timer_cnt_14_rstpottimer_cnt_141.5513.5375.088clk_main_BUFG30.569.5Paths for end point timer_cnt_15 (SLICE_X14Y43.B4), 39 paths 14.321tx_clk_count_8timer_cnt_155.3340.01020.0000.335tx_clk_count_8timer_cnt_154SLICE_X17Y40.CLKclk_main_BUFGSLICE_X17Y40.DQTcko0.430tx_clk_count<8>tx_clk_count_8SLICE_X17Y41.D2net30.934tx_clk_count<8>SLICE_X17Y41.DTilo0.259tx_clk_count<11>GND_1_o_GND_1_o_equal_10_o<11>2SLICE_X12Y39.A3net160.984GND_1_o_GND_1_o_equal_10_o<11>1SLICE_X12Y39.ATilo0.254tx_clk_count<0>GND_1_o_GND_1_o_equal_10_o<11>3SLICE_X19Y39.B5net90.767GND_1_o_GND_1_o_equal_10_oSLICE_X19Y39.BTilo0.259timer_cnt<22>_n03361SLICE_X14Y43.B4net121.098_n0336SLICE_X14Y43.CLKTas0.349timer_cnt<17>timer_cnt_15_rstpottimer_cnt_151.5513.7835.334clk_main_BUFG29.170.914.523tx_clk_count_7timer_cnt_155.1320.01020.0000.335tx_clk_count_7timer_cnt_154SLICE_X17Y40.CLKclk_main_BUFGSLICE_X17Y40.CQTcko0.430tx_clk_count<8>tx_clk_count_7SLICE_X17Y41.D1net30.732tx_clk_count<7>SLICE_X17Y41.DTilo0.259tx_clk_count<11>GND_1_o_GND_1_o_equal_10_o<11>2SLICE_X12Y39.A3net160.984GND_1_o_GND_1_o_equal_10_o<11>1SLICE_X12Y39.ATilo0.254tx_clk_count<0>GND_1_o_GND_1_o_equal_10_o<11>3SLICE_X19Y39.B5net90.767GND_1_o_GND_1_o_equal_10_oSLICE_X19Y39.BTilo0.259timer_cnt<22>_n03361SLICE_X14Y43.B4net121.098_n0336SLICE_X14Y43.CLKTas0.349timer_cnt<17>timer_cnt_15_rstpottimer_cnt_151.5513.5815.132clk_main_BUFG30.269.814.607tx_clk_count_1timer_cnt_155.0480.01020.0000.335tx_clk_count_1timer_cnt_154SLICE_X17Y39.CLKclk_main_BUFGSLICE_X17Y39.AQTcko0.430tx_clk_count<4>tx_clk_count_1SLICE_X17Y41.D3net30.648tx_clk_count<1>SLICE_X17Y41.DTilo0.259tx_clk_count<11>GND_1_o_GND_1_o_equal_10_o<11>2SLICE_X12Y39.A3net160.984GND_1_o_GND_1_o_equal_10_o<11>1SLICE_X12Y39.ATilo0.254tx_clk_count<0>GND_1_o_GND_1_o_equal_10_o<11>3SLICE_X19Y39.B5net90.767GND_1_o_GND_1_o_equal_10_oSLICE_X19Y39.BTilo0.259timer_cnt<22>_n03361SLICE_X14Y43.B4net121.098_n0336SLICE_X14Y43.CLKTas0.349timer_cnt<17>timer_cnt_15_rstpottimer_cnt_151.5513.4975.048clk_main_BUFG30.769.3Hold Paths: TS_clk_main = PERIOD TIMEGRP "clk_main" TS_osc HIGH 50%; Paths for end point data_tx_4 (SLICE_X18Y45.B6), 1 path 0.411data_buffer_rx_4_4data_tx_40.413-0.0020.0000.000data_buffer_rx_4_4data_tx_41SLICE_X19Y45.CLKclk_main_BUFGSLICE_X19Y45.AQTcko0.198data_buffer_rx_4<7>data_buffer_rx_4_4SLICE_X18Y45.B6net20.025data_buffer_rx_4<4>SLICE_X18Y45.CLKTah0.190data_tx<6>data_tx_4_dpot1data_tx_40.3880.0250.413clk_main_BUFG93.96.1Paths for end point data_buffer_rx_4_20 (SLICE_X22Y46.A6), 1 path 0.413data_buffer_rx_4_20data_buffer_rx_4_200.4130.0000.0000.000data_buffer_rx_4_20data_buffer_rx_4_201SLICE_X22Y46.CLKclk_main_BUFGSLICE_X22Y46.AQTcko0.200data_buffer_rx_4<23>data_buffer_rx_4_20SLICE_X22Y46.A6net20.023data_buffer_rx_4<20>SLICE_X22Y46.CLKTah0.190data_buffer_rx_4<23>data_buffer_rx_4_20_dpotdata_buffer_rx_4_200.3900.0230.413clk_main_BUFG94.45.6Paths for end point data_tx_3 (SLICE_X18Y45.A6), 1 path 0.414data_tx_3data_tx_30.4140.0000.0000.000data_tx_3data_tx_31SLICE_X18Y45.CLKclk_main_BUFGSLICE_X18Y45.AQTcko0.200data_tx<6>data_tx_3SLICE_X18Y45.A6net20.024data_tx<3>SLICE_X18Y45.CLKTah0.190data_tx<6>data_tx_3_dpot1data_tx_30.3900.0240.414clk_main_BUFG94.25.8Component Switching Limit Checks: TS_clk_main = PERIOD TIMEGRP "clk_main" TS_osc HIGH 50%;0oscosc5.83400007118010938.000125.000Fri Feb 13 14:07:19 2015 TraceTrace Settings Peak Memory Usage: 236 MB