Release 14.2 - xst P.28xd (nt64) Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.09 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.09 secs --> Reading design: top.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Parsing 3) HDL Elaboration 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Partition Report 8) Design Summary 8.1) Primitive and Black Box Usage 8.2) Device utilization summary 8.3) Partition Resource Summary 8.4) Timing Report 8.4.1) Clock Information 8.4.2) Asynchronous Control Signals Information 8.4.3) Timing Summary 8.4.4) Timing Details 8.4.5) Cross Clock Domains Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "top.prj" Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "top" Output Format : NGC Target Device : xc6slx9-2-tqg144 ---- Source Options Top Module Name : top Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : LUT RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Shift Register Extraction : YES ROM Style : Auto Resource Sharing : YES Asynchronous To Synchronous : NO Shift Register Minimum Size : 2 Use DSP Block : Auto Automatic Register Balancing : No ---- Target Options LUT Combining : Auto Reduce Control Sets : Auto Add IO Buffers : YES Global Maximum Fanout : 100000 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Optimize Instantiated Primitives : NO Use Clock Enable : Auto Use Synchronous Set : Auto Use Synchronous Reset : Auto Pack IO Registers into IOBs : Auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Power Reduction : NO Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 DSP48 Utilization Ratio : 100 Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Parsing * ========================================================================= Analyzing Verilog file "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\IR-Remote_Receiver\hextobcd.v" into library work Parsing module . Analyzing Verilog file "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\IR-Remote_Receiver\Printf.v" into library work Parsing module . Analyzing Verilog file "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\IR-Remote_Receiver\Lcd.v" into library work Parsing module . Analyzing Verilog file "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\IR-Remote_Receiver\IR_Receiver.v" into library work Parsing module . Analyzing Verilog file "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\IR-Remote_Receiver\top.v" into library work Parsing module . ========================================================================= * HDL Elaboration * ========================================================================= WARNING:HDLCompiler:1016 - "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\IR-Remote_Receiver\top.v" Line 106: Port CLK180 is not connected to this instance Elaborating module . Elaborating module . Elaborating module . WARNING:HDLCompiler:189 - "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\IR-Remote_Receiver\top.v" Line 126: Size mismatch in connection of port . Formal port size is 32-bit while actual signal size is 31-bit. Elaborating module . Elaborating module . Elaborating module . ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\IR-Remote_Receiver\top.v". S0 = 0 S1 = 1 S2 = 2 S3 = 3 S4 = 4 S5 = 5 S6 = 6 S7 = 7 S8 = 8 S9 = 9 S10 = 10 S11 = 11 S12 = 12 S13 = 13 Found 1-bit register for signal . Found 32-bit register for signal . Found 4-bit register for signal . Found 1-bit register for signal . Found 2-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 3 | | Clock | clk_main (rising_edge) | | Reset | reset (positive) | | Reset type | synchronous | | Reset State | 0000 | | Power Up State | 0000 | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 32-bit adder for signal created at line 84. Found 2-bit adder for signal created at line 99. Found 8-bit comparator equal for signal created at line 49 Summary: inferred 2 Adder/Subtractor(s). inferred 45 D-type flip-flop(s). inferred 1 Comparator(s). inferred 1 Finite State Machine(s). Unit synthesized. Synthesizing Unit . Related source file is "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\IR-Remote_Receiver\IR_Receiver.v". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal . Found 1-bit register for signal . Found 32-bit register for signal . Found 4-bit register for signal . Found 8-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Found finite state machine for signal . ----------------------------------------------------------------------- | States | 14 | | Transitions | 38 | | Inputs | 7 | | Outputs | 4 | | Clock | clk_main (rising_edge) | | Power Up State | 0000 | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 16-bit adder for signal created at line 132. Found 32-bit adder for signal created at line 203. Found 8-bit adder for signal created at line 235. Found 32-bit comparator greater for signal created at line 186 Found 32-bit comparator greater for signal created at line 186 Found 32-bit comparator lessequal for signal created at line 222 Found 32-bit comparator lessequal for signal created at line 222 Summary: inferred 3 Adder/Subtractor(s). inferred 155 D-type flip-flop(s). inferred 4 Comparator(s). inferred 8 Multiplexer(s). inferred 1 Finite State Machine(s). Unit synthesized. Synthesizing Unit . Related source file is "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\IR-Remote_Receiver\Printf.v". CLOCKS_PER_BIT = 2604 CLOCKS_WAIT_FOR_RECEIVE = 1302 MAX_TX_BIT_COUNT = 9 MAX_DATA_BUFFER_INDEX = 15 LCD_BLANK = 8'b00100000 LCD_DASH = 8'b00101101 LCD_COLON = 8'b00111010 LCD_PERIODE = 8'b00101110 LCD_EQUAL = 8'b00111101 LCD_0 = 8'b00110000 LCD_1 = 8'b00110001 LCD_2 = 8'b00110010 LCD_3 = 8'b00110011 LCD_4 = 8'b00110100 LCD_5 = 8'b00110101 LCD_6 = 8'b00110110 LCD_7 = 8'b00110111 LCD_8 = 8'b00111000 LCD_9 = 8'b00111001 LCD_A = 8'b01000001 LCD_B = 8'b01000010 LCD_C = 8'b01000011 LCD_D = 8'b01000100 LCD_E = 8'b01000101 LCD_F = 8'b01000110 LCD_G = 8'b01000111 LCD_H = 8'b01001000 LCD_I = 8'b01001001 LCD_J = 8'b01001010 LCD_K = 8'b01001011 LCD_L = 8'b01001100 LCD_M = 8'b01001101 LCD_N = 8'b01001110 LCD_O = 8'b01001111 LCD_P = 8'b01010000 LCD_Q = 8'b01010001 LCD_R = 8'b01010010 LCD_S = 8'b01010011 LCD_T = 8'b01010100 LCD_U = 8'b01010101 LCD_V = 8'b01010110 LCD_W = 8'b01010111 LCD_X = 8'b01011000 LCD_Y = 8'b01011001 LCD_Z = 8'b01011010 LCD_UNDER = 8'b01011111 LCD_S_a = 8'b01100001 LCD_S_b = 8'b01100010 LCD_S_c = 8'b01100011 LCD_S_d = 8'b01100100 LCD_S_e = 8'b01100101 LCD_S_f = 8'b01100110 LCD_S_g = 8'b01100111 LCD_S_h = 8'b01101000 LCD_S_i = 8'b01101001 LCD_S_j = 8'b01101010 LCD_S_k = 8'b01101011 LCD_S_l = 8'b01101100 LCD_S_m = 8'b01101101 LCD_S_n = 8'b01101110 LCD_S_o = 8'b01101111 LCD_S_p = 8'b01110000 LCD_S_q = 8'b01110001 LCD_S_r = 8'b01110010 LCD_S_s = 8'b01110011 LCD_S_t = 8'b01110100 LCD_S_u = 8'b01110101 LCD_S_v = 8'b01110110 LCD_S_w = 8'b01110111 LCD_S_x = 8'b01111000 LCD_S_y = 8'b01111001 LCD_S_z = 8'b01111010 LCD_dot = 8'b01100000 Found 4-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 19-bit register for signal . Found 8-bit register for signal . Found 16-bit register for signal . Found 4-bit adder for signal created at line 170. Found 8-bit adder for signal created at line 174. Found 16-bit adder for signal created at line 185. Found 19-bit adder for signal created at line 188. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 7-bit adder for signal created at line 135. Found 7-bit adder for signal created at line 137. Found 3-bit subtractor for signal > created at line 169. Found 1-bit 8-to-1 multiplexer for signal created at line 169. Found 19-bit comparator greater for signal created at line 156 Found 4-bit comparator greater for signal created at line 168 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Found 4-bit comparator lessequal for signal created at line 134 Summary: inferred 25 Adder/Subtractor(s). inferred 56 D-type flip-flop(s). inferred 12 Comparator(s). inferred 16 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\IR-Remote_Receiver\hextobcd.v". Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 55. Found 4-bit adder for signal created at line 57. Found 4-bit adder for signal created at line 59. Found 4-bit adder for signal created at line 61. Found 4-bit adder for signal created at line 63. Found 4-bit adder for signal created at line 65. Found 3-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal created at line 64 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 54 Found 4-bit comparator greater for signal created at line 56 Found 4-bit comparator greater for signal created at line 58 Found 4-bit comparator greater for signal created at line 60 Found 4-bit comparator greater for signal created at line 62 Found 4-bit comparator greater for signal