//! **************************************************************************
// Written by: Map P.28xd on Thu Feb 12 22:11:27 2015
//! **************************************************************************

SCHEMATIC START;
COMP "BT_RX" LOCATE = SITE "P112" LEVEL 1;
COMP "BT_TX" LOCATE = SITE "P114" LEVEL 1;
COMP "osc" LOCATE = SITE "P50" LEVEL 1;
PIN SP6_BUFIO_INSERT_ML_BUFIO2_0_pins<0> = BEL "SP6_BUFIO_INSERT_ML_BUFIO2_0"
        PINNAME DIVCLK;
PIN DCM_SP_1_pins<3> = BEL "DCM_SP_1" PINNAME CLKIN;
TIMEGRP tnm_osc = BEL "reset_cnt_0" BEL "reset_cnt_1" BEL "reset" PIN
        "SP6_BUFIO_INSERT_ML_BUFIO2_0_pins<0>" PIN "DCM_SP_1_pins<3>";
PIN HC02_Mram_data_buffer_index[6]_X_3_o_wide_mux_5_OUT_pins<10> = BEL
        "HC02_Mram_data_buffer_index[6]_X_3_o_wide_mux_5_OUT" PINNAME
        CLKAWRCLK;
TIMEGRP clk_main = BEL "HC02/data_tx_7" BEL "HC02/data_tx_6" BEL
        "HC02/data_tx_5" BEL "HC02/data_tx_4" BEL "HC02/data_tx_3" BEL
        "HC02/data_tx_2" BEL "HC02/data_tx_1" BEL "HC02/data_tx_0" BEL
        "HC02/data_buffer_index_7" BEL "HC02/data_buffer_index_6" BEL
        "HC02/data_buffer_index_5" BEL "HC02/data_buffer_index_4" BEL
        "HC02/data_buffer_index_3" BEL "HC02/data_buffer_index_2" BEL
        "HC02/data_buffer_index_0" BEL "HC02/tx_bit_count_3" BEL
        "HC02/tx_bit_count_2" BEL "HC02/tx_bit_count_1" BEL
        "HC02/tx_bit_count_0" BEL "HC02/timer_cnt_setup_13" BEL
        "HC02/timer_cnt_setup_7" BEL "HC02/timer_cnt_setup_5" BEL
        "clk_main_BUFG" BEL "HC02/tx_bit" BEL "HC02/sel_mux" BEL
        "HC02/tx_clk_count_0" BEL "HC02/tx_clk_count_10" BEL
        "HC02/tx_clk_count_9" BEL "HC02/tx_clk_count_8" BEL
        "HC02/tx_clk_count_7" BEL "HC02/tx_clk_count_6" BEL
        "HC02/tx_clk_count_5" BEL "HC02/tx_clk_count_4" BEL
        "HC02/tx_clk_count_3" BEL "HC02/tx_clk_count_2" BEL
        "HC02/tx_clk_count_1" BEL "HC02/data_buffer_index_1" BEL
        "HC02/timer_cnt_31" BEL "HC02/timer_cnt_30" BEL "HC02/timer_cnt_29"
        BEL "HC02/timer_cnt_28" BEL "HC02/timer_cnt_27" BEL
        "HC02/timer_cnt_26" BEL "HC02/timer_cnt_25" BEL "HC02/timer_cnt_24"
        BEL "HC02/timer_cnt_23" BEL "HC02/timer_cnt_22" BEL
        "HC02/timer_cnt_21" BEL "HC02/timer_cnt_20" BEL "HC02/timer_cnt_19"
        BEL "HC02/timer_cnt_18" BEL "HC02/timer_cnt_17" BEL
        "HC02/timer_cnt_16" BEL "HC02/timer_cnt_15" BEL "HC02/timer_cnt_14"
        BEL "HC02/timer_cnt_13" BEL "HC02/timer_cnt_12" BEL
        "HC02/timer_cnt_11" BEL "HC02/timer_cnt_10" BEL "HC02/timer_cnt_9" BEL
        "HC02/timer_cnt_8" BEL "HC02/timer_cnt_7" BEL "HC02/timer_cnt_6" BEL
        "HC02/timer_cnt_5" BEL "HC02/timer_cnt_4" BEL "HC02/timer_cnt_3" BEL
        "HC02/timer_cnt_2" BEL "HC02/timer_cnt_1" BEL "HC02/timer_cnt_0" PIN
        "HC02_Mram_data_buffer_index[6]_X_3_o_wide_mux_5_OUT_pins<10>";
TS_osc = PERIOD TIMEGRP "tnm_osc" 20 ns HIGH 50%;
TS_clk_main = PERIOD TIMEGRP "clk_main" TS_osc HIGH 50%;
SCHEMATIC END;