`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   12:58:01 12/30/2014
// Design Name:   Bluetooth
// Module Name:   H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/LED_14_1225/LED_14_1224/TEST/HC02_Testbench.v
// Project Name:  TEST
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Bluetooth
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module HC02_Testbench;

	// Inputs
	reg clk;
	reg reset;
	reg rxd;

	// Outputs
	wire txd;

	// Instantiate the Unit Under Test (UUT)
	Bluetooth uut (
		.clk(clk), 
		.reset(reset), 
		.rxd(rxd), 
		.txd(txd)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 1;
		rxd = 0;

		// Wait 100 ns for global reset to finish
		#100;
      reset = 0;  
		// Add stimulus here

	end
	
	always
	begin
	#20 clk = ~clk;
	end 
      
endmodule