top Project Status (02/04/2015 - 11:15:38)
Project File: Fnd-7Segment.xise Parser Errors: No Errors
Module Name: top Implementation State: Translated (Failed)
Target Device: xc6slx9-2tqg144
  • Errors:
 X 1 Error (0 new)
Product Version:ISE 14.2
  • Warnings:
 2 Warnings (1 new)
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
   
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of bonded IOBs 0 102 0%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentΌφ 2 4 11:15:26 201501 Warning (1 new)0
Translation ReportCurrentΌφ 2 4 11:15:37 2015X 1 Error (0 new)1 Warning (0 new)0
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 02/04/2015 - 11:15:53