Release 14.2 - xst P.28xd (nt64) Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.08 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.08 secs --> Reading design: top.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Parsing 3) HDL Elaboration 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Partition Report 8) Design Summary 8.1) Primitive and Black Box Usage 8.2) Device utilization summary 8.3) Partition Resource Summary 8.4) Timing Report 8.4.1) Clock Information 8.4.2) Asynchronous Control Signals Information 8.4.3) Timing Summary 8.4.4) Timing Details 8.4.5) Cross Clock Domains Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "top.prj" Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "top" Output Format : NGC Target Device : xc6slx9-2-tqg144 ---- Source Options Top Module Name : top Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : LUT RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Shift Register Extraction : YES ROM Style : Auto Resource Sharing : YES Asynchronous To Synchronous : NO Shift Register Minimum Size : 2 Use DSP Block : Auto Automatic Register Balancing : No ---- Target Options LUT Combining : Auto Reduce Control Sets : Auto Add IO Buffers : YES Global Maximum Fanout : 100000 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Optimize Instantiated Primitives : NO Use Clock Enable : Auto Use Synchronous Set : Auto Use Synchronous Reset : Auto Pack IO Registers into IOBs : Auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Power Reduction : NO Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 DSP48 Utilization Ratio : 100 Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Parsing * ========================================================================= Analyzing Verilog file "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Fnd-7Segment\hextobcd.v" into library work Parsing module . Analyzing Verilog file "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Fnd-7Segment\top.v" into library work Parsing module . ========================================================================= * HDL Elaboration * ========================================================================= Elaborating module . Elaborating module . ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Fnd-7Segment\top.v". char_0 = 8'b00111111 char_1 = 8'b00000110 char_2 = 8'b01011011 char_3 = 8'b01001111 char_4 = 8'b01100110 char_5 = 8'b01101101 char_6 = 8'b01111101 char_7 = 8'b00100111 char_8 = 8'b01111111 char_9 = 8'b01101111 Found 16-bit register for signal . Found 23-bit register for signal . Found 14-bit register for signal . Found 4-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 2-bit register for signal . Found 2-bit adder for signal created at line 78. Found 16-bit adder for signal created at line 97. Found 23-bit adder for signal created at line 111. Found 14-bit adder for signal created at line 130. Found 16x8-bit Read Only RAM for signal Found 16x8-bit Read Only RAM for signal Found 16x8-bit Read Only RAM for signal Found 16x8-bit Read Only RAM for signal Summary: inferred 4 RAM(s). inferred 4 Adder/Subtractor(s). inferred 68 D-type flip-flop(s). inferred 4 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Fnd-7Segment\hextobcd.v". Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 4-bit adder for signal created at line 37. Found 4-bit adder for signal created at line 39. Found 4-bit adder for signal created at line 41. Found 4-bit adder for signal created at line 43. Found 4-bit adder for signal created at line 45. Found 4-bit adder for signal created at line 47. Found 4-bit adder for signal created at line 49. Found 4-bit adder for signal created at line 51. Found 4-bit adder for signal created at line 53. Found 3-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Found 4-bit comparator greater for signal created at line 36 Found 4-bit comparator greater for signal created at line 38 Found 4-bit comparator greater for signal created at line 40 Found 4-bit comparator greater for signal created at line 42 Found 4-bit comparator greater for signal created at line 44 Found 4-bit comparator greater for signal created at line 46 Found 4-bit comparator greater for signal created at line 48 Found 4-bit comparator greater for signal created at line 50 Found 4-bit comparator greater for signal created at line 52 Summary: inferred 252 Adder/Subtractor(s). inferred 252 Comparator(s). inferred 981 Multiplexer(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # RAMs : 4 16x8-bit single-port Read Only RAM : 4 # Adders/Subtractors : 256 14-bit adder : 1 16-bit adder : 1 2-bit adder : 1 23-bit adder : 1 4-bit adder : 252 # Registers : 7 1-bit register : 1 14-bit register : 1 16-bit register : 1 2-bit register : 1 23-bit register : 1 4-bit register : 1 8-bit register : 1 # Comparators : 252 3-bit comparator greater : 1 4-bit comparator greater : 251 # Multiplexers : 985 1-bit 2-to-1 multiplexer : 980 14-bit 2-to-1 multiplexer : 1 16-bit 2-to-1 multiplexer : 1 23-bit 2-to-1 multiplexer : 1 4-bit 2-to-1 multiplexer : 1 40-bit 2-to-1 multiplexer : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 16-word x 8-bit | | | weA | connected to signal | high | | addrA | connected to signal > | | | diA | connected to signal | | | doA | connected to signal | | ----------------------------------------------------------------------- INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 16-word x 8-bit | | | weA | connected to signal | high | | addrA | connected to signal > | | | diA | connected to signal | | | doA | connected to signal | | ----------------------------------------------------------------------- INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 16-word x 8-bit | | | weA | connected to signal | high | | addrA | connected to signal > | | | diA | connected to signal | | | doA | connected to signal | | ----------------------------------------------------------------------- INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 16-word x 8-bit | | | weA | connected to signal | high | | addrA | connected to signal > | | | diA | connected to signal | | | doA | connected to signal | | ----------------------------------------------------------------------- Unit synthesized (advanced). ========================================================================= Advanced HDL Synthesis Report Macro Statistics # RAMs : 4 16x8-bit single-port distributed Read Only RAM : 4 # Adders/Subtractors : 252 3-bit adder : 24 4-bit adder : 228 # Counters : 4 14-bit up counter : 1 16-bit up counter : 1 2-bit up counter : 1 23-bit up counter : 1 # Registers : 13 Flip-Flops : 13 # Comparators : 252 3-bit comparator greater : 1 4-bit comparator greater : 251 # Multiplexers : 982 1-bit 2-to-1 multiplexer : 980 4-bit 2-to-1 multiplexer : 1 40-bit 2-to-1 multiplexer : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. Optimizing unit ... Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 5. FlipFlop fnd_cnt_11 has been replicated 1 time(s) FlipFlop fnd_cnt_12 has been replicated 2 time(s) Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 70 Flip-Flops : 70 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Design Summary * ========================================================================= Top Level Output File Name : top.ngc Primitive and Black Box Usage: ------------------------------ # BELS : 383 # GND : 1 # INV : 4 # LUT1 : 50 # LUT2 : 18 # LUT3 : 5 # LUT4 : 19 # LUT5 : 90 # LUT6 : 84 # MUXCY : 50 # MUXF7 : 8 # VCC : 1 # XORCY : 53 # FlipFlops/Latches : 70 # FD : 1 # FDC : 39 # FDCE : 20 # FDE : 2 # FDPE : 1 # FDR : 7 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 12 # OBUF : 12 Device utilization summary: --------------------------- Selected Device : 6slx9tqg144-2 Slice Logic Utilization: Number of Slice Registers: 70 out of 11440 0% Number of Slice LUTs: 270 out of 5720 4% Number used as Logic: 270 out of 5720 4% Slice Logic Distribution: Number of LUT Flip Flop pairs used: 285 Number with an unused Flip Flop: 215 out of 285 75% Number with an unused LUT: 15 out of 285 5% Number of fully used LUT-FF pairs: 55 out of 285 19% Number of unique control sets: 6 IO Utilization: Number of IOs: 13 Number of bonded IOBs: 13 out of 102 12% Specific Feature Utilization: Number of BUFG/BUFGCTRLs: 1 out of 16 6% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= Timing Report NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ osc | BUFGP | 70 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -2 Minimum period: 13.114ns (Maximum Frequency: 76.254MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 4.380ns Maximum combinational path delay: No path found Timing Details: --------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'osc' Clock period: 13.114ns (frequency: 76.254MHz) Total number of paths / destination ports: 558201 / 160 ------------------------------------------------------------------------- Delay: 13.114ns (Levels of Logic = 10) Source: fnd_cnt_10 (FF) Destination: SEG_1 (FF) Source Clock: osc rising Destination Clock: osc rising Data Path: fnd_cnt_10 to SEG_1 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE:C->Q 12 0.525 1.297 fnd_cnt_10 (fnd_cnt_10) LUT5:I2->O 10 0.235 1.236 hextobcd1/Mmux_hex[11]_hex[12]_MUX_797_o11 (hextobcd1/Madd_hex[11]_GND_2_o_add_362_OUT_lut<3>) LUT6:I3->O 10 0.235 1.236 hextobcd1/Mmux_hex[9]_hex[10]_MUX_869_o12 (hextobcd1/Madd_hex[9]_GND_2_o_add_398_OUT_lut<3>) LUT6:I3->O 3 0.235 0.874 hextobcd1/GND_2_o_hex[6]_LessThan_452_o_SW1_SW0 (N130) LUT5:I3->O 1 0.250 1.112 hextobcd1/GND_2_o_hex[6]_LessThan_452_o_SW4 (N40) LUT5:I0->O 11 0.254 1.039 hextobcd1/GND_2_o_hex[6]_LessThan_452_o (hextobcd1/GND_2_o_hex[6]_LessThan_452_o) LUT6:I5->O 8 0.254 1.052 hextobcd1/Mmux_hex[5]_hex[5]_MUX_1048_o11 (hextobcd1/Madd_hex[8]_GND_2_o_add_490_OUT_cy<0>) LUT5:I3->O 1 0.250 0.790 segment_r<1>22_SW1 (N38) LUT5:I3->O 2 0.250 0.726 segment_r<1>22 (segment_r<1>22) LUT6:I5->O 1 0.254 0.682 segment_r<1>24 (segment_r<1>2) LUT5:I4->O 1 0.254 0.000 segment_r<1>6 (segment_r<1>) FDR:D 0.074 SEG_1 ---------------------------------------- Total 13.114ns (3.070ns logic, 10.044ns route) (23.4% logic, 76.6% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'osc' Total number of paths / destination ports: 11 / 11 ------------------------------------------------------------------------- Offset: 4.380ns (Levels of Logic = 1) Source: digit_2 (FF) Destination: CA<2> (PAD) Source Clock: osc rising Data Path: digit_2 to CA<2> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE:C->Q 8 0.525 0.943 digit_2 (digit_2) OBUF:I->O 2.912 CA_2_OBUF (CA<2>) ---------------------------------------- Total 4.380ns (3.437ns logic, 0.943ns route) (78.5% logic, 21.5% route) ========================================================================= Cross Clock Domains Report: -------------------------- Clock to Setup on destination clock osc ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ osc | 13.114| | | | ---------------+---------+---------+---------+---------+ ========================================================================= Total REAL time to Xst completion: 14.00 secs Total CPU time to Xst completion: 13.73 secs --> Total memory usage is 273288 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 4 ( 0 filtered)