`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:20:38 02/04/2015
// Design Name:   top
// Module Name:   H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/Fnd-7Segment/testbench.v
// Project Name:  Fnd-7Segment
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: top
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module testbench;

	// Inputs
	reg osc;

	// Outputs
	wire [7:0] Segment;
	wire [3:0] Cathode;

	// Instantiate the Unit Under Test (UUT)
	top uut (
		.osc(osc), 
		.Segment(Segment), 
		.Cathode(Cathode)
	);

	initial begin
		// Initialize Inputs
		osc = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
	always
	#10 osc = ~osc;
      
endmodule