INTSTYLE=ise
INFILE=H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Encoder_Rotary\top.ncd
OUTFILE=H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Encoder_Rotary\top.bit
FAMILY=Spartan6
PART=xc6slx9-2tqg144
WORKINGDIR=H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\Encoder_Rotary
LICENSE=WebPack
USER_INFO=__0_0_0