`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:53:56 02/13/2015 
// Design Name: 
// Module Name:    top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module top(
	input osc,
	//	input enc_z,
	input enc_b,
	input enc_a,
	output lcd_rs,
	output lcd_en,
	output [7:0]lcd_data
    );
wire clk_main;
wire [31:0]x_encoder_w;
wire clk_fb, clk_fb2;
reg [1:0]reset_cnt = 0;
reg reset = 1'b1;

reg enc_a1=0;
reg enc_a2=0;
reg enc_a3=0;
reg enc_b1=0;
reg enc_b2=0;
reg enc_b3=0;
wire enc_a_real;
wire enc_b_real;
always@(posedge clk_main)
enc_a1 <= enc_a;
always@(posedge clk_main)
enc_a2 <= enc_a1;
always@(posedge clk_main)
enc_a3 <= enc_a2;

always@(posedge clk_main)
enc_b1 <= enc_b;
always@(posedge clk_main)
enc_b2 <= enc_b1;
always@(posedge clk_main)
enc_b3 <= enc_b2;

assign enc_a_real = (enc_a1 & enc_a2 & enc_a3);
assign enc_b_real = (enc_b1 & enc_b2 & enc_b3);


parameter S0=0, S1=1, S2=2, S3=3, S4=4, S5=5, S6=6, S7=7, S8=8, S9=9, S10=10, S11=11, S12=12, S13=13;
always@(posedge clk_main)
begin
	if(reset==1'b1)
	begin
	reset_cnt <= reset_cnt + 1'b1;
	end 
	if(reset_cnt==2)
	begin
	reset <= 1'b0;
	end
end 
Encoder_Read enc
 (
	.rotary_a(enc_a_real),
	.rotary_b(enc_b_real),
	.clk(clk_main),
	.reset(reset),
	//  .event_en(event_en0),
	//	 .event_left(event_left0),
	//  .event_right(event_right0),
	.enc_value(x_encoder_w),
	.dir()
    ); 
LCD TextLcd
(
	.clk(clk_main),
	.reset(reset),	 
	.rs(lcd_rs),
	.en(lcd_en),
	.data(lcd_data),
	.enc_v(x_encoder_w[31:0])
);
DCM_SP #(
    .CLKIN_PERIOD       (20),
    .CLKFX_DIVIDE	    (2),	
    .CLKFX_MULTIPLY   (2),
    .CLKDV_DIVIDE       (2.0),
    .CLK_FEEDBACK       ("1X")
)
DCM_SP_1 (
    .CLKIN    (osc),
    .CLKFB    (clk_fb),
    .CLK0     (clk_fb),
    .RST      (1'b0),
    .CLKFX    (clk_main),
    .PSEN     (1'b0)
);
endmodule