top Project Status (02/04/2015 - 17:37:39)
Project File: DCMotor.xise Parser Errors: No Errors
Module Name: top Implementation State: Synthesized
Target Device: xc6slx9-2tqg144
  • Errors:
  
Product Version:ISE 14.2
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentΌφ 2 4 17:32:25 2015   
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentΌφ 2 4 17:37:34 2015
WebTalk Log FileCurrentΌφ 2 4 17:37:39 2015

Date Generated: 02/04/2015 - 17:37:39