xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/DCMotor/DcMotor.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/DCMotor/DcMotor.syr" 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/DCMotor/DcMotor.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/DCMotor/DcMotor.syr" 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/DCMotor/DcMotor.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/DCMotor/DcMotor.syr" 
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc top.ucf -p xc6slx9-tqg144-2 DcMotor.ngc DcMotor.ngd  
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o DcMotor_map.ncd DcMotor.ngd DcMotor.pcf 
par -w -intstyle ise -ol high -mt off DcMotor_map.ncd DcMotor.ncd DcMotor.pcf 
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml DcMotor.twx DcMotor.ncd -o DcMotor.twr DcMotor.pcf -ucf top.ucf 
bitgen -intstyle ise -f DcMotor.ut DcMotor.ncd 
xst -intstyle ise -ifn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/DCMotor/DcMotor.xst" -ofn "H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/DCMotor/DcMotor.syr" 
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc top.ucf -p xc6slx9-tqg144-2 DcMotor.ngc DcMotor.ngd  
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o DcMotor_map.ncd DcMotor.ngd DcMotor.pcf 
par -w -intstyle ise -ol high -mt off DcMotor_map.ncd DcMotor.ncd DcMotor.pcf 
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml DcMotor.twx DcMotor.ncd -o DcMotor.twr DcMotor.pcf -ucf top.ucf 
bitgen -intstyle ise -f DcMotor.ut DcMotor.ncd