`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   10:17:38 02/04/2015
// Design Name:   top
// Module Name:   H:/Product/LK/FPGA/LK-Xilinx-TB/VerilogHDL/3by3_SWITCH/Switch/Testbench.v
// Project Name:  Switch
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: top
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Testbench;

	// Inputs
	reg osc;
	reg SW_INPUT0;
	reg SW_INPUT1;
	reg SW_INPUT2;

	// Outputs
	wire [7:0] LED;
	wire SW_COMMON0;
	wire SW_COMMON1;
	wire SW_COMMON2;

	// Instantiate the Unit Under Test (UUT)
	top uut (
		.osc(osc), 
		.LED(LED), 
		.SW_INPUT0(SW_INPUT0), 
		.SW_INPUT1(SW_INPUT1), 
		.SW_INPUT2(SW_INPUT2), 
		.SW_COMMON0(SW_COMMON0), 
		.SW_COMMON1(SW_COMMON1), 
		.SW_COMMON2(SW_COMMON2)
	);

	initial begin
		// Initialize Inputs
		osc = 0;
		SW_INPUT0 = 0;
		SW_INPUT1 = 0;
		SW_INPUT2 = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
	always #10 osc = ~osc;
      
endmodule