<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
     changes made to this file may result in unpredictable
     behavior or data corruption.  It is strongly advised that
     users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">RXD_IBUF</arg> has no load.  PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="468" delta="old" >Your design did not meet timing.  The following are some suggestions to assist you to meet timing in your design.

Review the timing report using Timing Analyzer (In ISE select &quot;Post-Place &amp;
Route Static Timing Report&quot;). Go to the failing constraint(s) and evaluate the failing paths for each constraint.

Try the Design Goal and Strategies for Timing Performance(In ISE select Project -&gt; Design Goals &amp; Strategies) to ensure the best options are set in the tools for timing closure.

</msg>

<msg type="warning" file="ParHelpers" num="361" delta="old" >There are <arg fmt="%d" index="1">1</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

</msg>

<msg type="warning" file="Par" num="283" delta="old" >There are <arg fmt="%d" index="1">1</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

</msg>

</messages>

