"H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\top.v" Line 45: Port CLK180 is not connected to this instance "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\top.v" Line 75: Port reset_start is not connected to this instance "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\LCD.v" Line 137: Result of 10-bit expression is truncated to fit in 9-bit target. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\LCD.v" Line 231: Result of 32-bit expression is truncated to fit in 1-bit target. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\hextobcd.v" Line 41: Assignment to bcd ignored, since the identifier is never used "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\hextobcd.v" Line 74: Result of 40-bit expression is truncated to fit in 16-bit target. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\LCD.v" Line 261: Size mismatch in connection of port <hex>. Formal port size is 16-bit while actual signal size is 4-bit. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\LCD.v" Line 262: Size mismatch in connection of port <bcdout>. Formal port size is 16-bit while actual signal size is 40-bit. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\LCD.v" Line 266: Size mismatch in connection of port <hex>. Formal port size is 16-bit while actual signal size is 4-bit. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\LCD.v" Line 267: Size mismatch in connection of port <bcdout>. Formal port size is 16-bit while actual signal size is 40-bit. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\LCD.v" Line 272: Size mismatch in connection of port <hex>. Formal port size is 16-bit while actual signal size is 4-bit. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\LCD.v" Line 273: Size mismatch in connection of port <bcdout>. Formal port size is 16-bit while actual signal size is 40-bit. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\LCD.v" Line 277: Size mismatch in connection of port <hex>. Formal port size is 16-bit while actual signal size is 4-bit. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\LCD.v" Line 278: Size mismatch in connection of port <bcdout>. Formal port size is 16-bit while actual signal size is 40-bit. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\LCD.v" Line 284: Size mismatch in connection of port <hex>. Formal port size is 16-bit while actual signal size is 4-bit. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\LCD.v" Line 285: Size mismatch in connection of port <bcdout>. Formal port size is 16-bit while actual signal size is 40-bit. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\LCD.v" Line 289: Size mismatch in connection of port <hex>. Formal port size is 16-bit while actual signal size is 1-bit. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\LCD.v" Line 290: Size mismatch in connection of port <bcdout>. Formal port size is 16-bit while actual signal size is 40-bit. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\top.v" Line 71: Size mismatch in connection of port <hour>. Formal port size is 32-bit while actual signal size is 8-bit. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\I2C.v" Line 64: Assignment to startbit_r ignored, since the identifier is never used "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\I2C.v" Line 662: Result of 9-bit expression is truncated to fit in 8-bit target. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\I2C.v" Line 664: Result of 9-bit expression is truncated to fit in 8-bit target. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\top.v" line 75: Output port <reset_start> of the instance <RTC1307> is unconnected or connected to loadless signal. "H:\Product\LK\FPGA\LK-Xilinx-TB\VerilogHDL\RealTimeClock1307\top.v" line 75: Output port <reset_state_w> of the instance <RTC1307> is unconnected or connected to loadless signal. Input <hour<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Node <hour_5> of sequential type is unconnected in block <RTC1307>. Node <hour_6> of sequential type is unconnected in block <RTC1307>. Node <hour_7> of sequential type is unconnected in block <RTC1307>. Node <RTC1307/hour_7> of sequential type is unconnected in block <top>. Node <RTC1307/hour_6> of sequential type is unconnected in block <top>. Node <RTC1307/hour_5> of sequential type is unconnected in block <top>. FF/Latch <TLCD/cnt_hz_16> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TLCD/cnt_hz_17> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TLCD/cnt_hz_18> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TLCD/cnt_hz_19> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TLCD/cnt_hz_20> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TLCD/cnt_hz_21> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TLCD/cnt_hz_22> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TLCD/cnt_hz_23> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TLCD/cnt_hz_24> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TLCD/cnt_hz_25> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TLCD/cnt_hz_26> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TLCD/cnt_hz_27> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TLCD/cnt_hz_28> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TLCD/cnt_hz_29> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TLCD/cnt_hz_30> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TLCD/cnt_hz_31> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RTC1307/read_sda8_cnt_2> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RTC1307/read_sda8_cnt_3> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RTC1307/read_sda8_cnt_4> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RTC1307/read_sda8_cnt_5> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RTC1307/read_sda8_cnt_6> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RTC1307/read_sda8_cnt_7> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process. The FF/Latch <RTC1307/clk_reset_0> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_0> The FF/Latch <RTC1307/clk_reset_1> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_1> The FF/Latch <RTC1307/clk_reset_2> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_2> The FF/Latch <RTC1307/clk_reset_3> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_3> The FF/Latch <RTC1307/clk_reset_4> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_4> The FF/Latch <RTC1307/clk_reset_5> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_5> The FF/Latch <RTC1307/clk_reset_6> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_6> The FF/Latch <RTC1307/clk_reset_7> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_7> The FF/Latch <RTC1307/clk_reset_8> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_8> The FF/Latch <RTC1307/clk_reset_9> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_9> The FF/Latch <RTC1307/clk_reset_10> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_10> The FF/Latch <RTC1307/clk_reset_11> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_11> The FF/Latch <RTC1307/clk_reset_12> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_12> The FF/Latch <RTC1307/clk_reset_13> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_13> The FF/Latch <RTC1307/clk_reset_14> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_14> The FF/Latch <RTC1307/clk_reset_15> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/cnt_reset2_15> The FF/Latch <RTC1307/state_write_sda_FSM_FFd36> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <RTC1307/clk_state_FSM_FFd23>