Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.2 (WebPack) - P.28xd Target Family: Spartan3
OS Platform: NT64 Target Device: xc3s200
Project ID (random number) ea081235f4e2469da4cf3e33d5a71d61.24F03BEC37754E5D93498E51C9A3D99B.13 Target Package: tq144
Registration ID __0_0_0 Target Speed: -4
Date Generated 2015-04-18T09:34:45 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i5-4670 CPU @ 3.40GHz CPU Speed 3392 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=171
  • 16-bit adder=2
  • 4-bit adder=147
  • 6-bit adder carry out=20
  • 8-bit adder=2
 Comparators=165
  • 16-bit comparator greatequal=5
  • 19-bit comparator greater=1
  • 19-bit comparator lessequal=1
  • 4-bit comparator greatequal=1
  • 4-bit comparator greater=144
  • 5-bit comparator greater=1
  • 5-bit comparator lessequal=11
  • 8-bit comparator greatequal=1
 Counters=5
  • 19-bit up counter=1
  • 2-bit up counter=1
  • 32-bit up counter=1
  • 8-bit up counter=2
 FSMs=1 Multiplexers=1
  • 8-bit 24-to-1 multiplexer=1
 Multipliers=1
  • 16x10-bit multiplier=1
 Registers=112
  • Flip-Flops=112
 		MiscellaneousStatistics
  • AGG_BONDED_IO=4
  • AGG_IO=4
  • AGG_SLICE=396
  • NUM_4_INPUT_LUT=715
  • NUM_BONDED_IOB=4
  • NUM_BUFGMUX=1
  • NUM_CYMUX=145
  • NUM_DCM=1
  • NUM_LUT_RT=105
  • NUM_MULT18X18=1
  • NUM_SLICEL=396
  • NUM_SLICE_FF=214
  • NUM_XOR=99
 		NetStatistics
  • NumNets_Active=654
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMDUMMY=16
  • NumNodesOfType_Active_CLKPIN=141
  • NumNodesOfType_Active_CNTRLPIN=116
  • NumNodesOfType_Active_DOUBLE=1972
  • NumNodesOfType_Active_DUMMY=2275
  • NumNodesOfType_Active_DUMMYBANK=2
  • NumNodesOfType_Active_DUMMYESC=2
  • NumNodesOfType_Active_GLOBAL=44
  • NumNodesOfType_Active_HFULLHEX=8
  • NumNodesOfType_Active_HLONG=2
  • NumNodesOfType_Active_HUNIHEX=117
  • NumNodesOfType_Active_INPUT=2514
  • NumNodesOfType_Active_IOBOUTPUT=2
  • NumNodesOfType_Active_OMUX=767
  • NumNodesOfType_Active_OUTPUT=652
  • NumNodesOfType_Active_PREBXBY=150
  • NumNodesOfType_Active_VFULLHEX=38
  • NumNodesOfType_Active_VLONG=1
  • NumNodesOfType_Active_VUNIHEX=58
  • NumNodesOfType_Gnd_BRAMDUMMY=15
  • NumNodesOfType_Gnd_CNTRLPIN=2
  • NumNodesOfType_Gnd_DOUBLE=16
  • NumNodesOfType_Gnd_DUMMYBANK=2
  • NumNodesOfType_Gnd_INPUT=30
  • NumNodesOfType_Gnd_OMUX=16
  • NumNodesOfType_Gnd_OUTPUT=12
  • NumNodesOfType_Gnd_PREBXBY=15
  • NumNodesOfType_Gnd_VFULLHEX=1
 SiteStatistics
  • IOB-DIFFM=2
  • IOB-DIFFS=2
  • SLICEL-SLICEM=212
 		SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • DCM=1
  • DCM_DCM=1
  • IOB=4
  • IOB_INBUF=3
  • IOB_OUTBUF=2
  • IOB_PAD=4
  • MULT18X18=1
  • MULT18X18_BLACKBOX=1
  • SLICEL=396
  • SLICEL_C1VDD=14
  • SLICEL_C2VDD=14
  • SLICEL_CYMUXF=76
  • SLICEL_CYMUXG=69
  • SLICEL_F=362
  • SLICEL_F5MUX=134
  • SLICEL_F6MUX=5
  • SLICEL_FFX=103
  • SLICEL_FFY=111
  • SLICEL_G=353
  • SLICEL_GNDF=62
  • SLICEL_GNDG=55
  • SLICEL_XORF=50
  • SLICEL_XORG=49
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
 BUFIO2FB_BUFIO2FB
  • DIVIDE_BYPASS=[TRUE:1]
  • INVERT_INPUTS=[FALSE:1]
 BUFIO2_BUFIO2
  • DIVIDE=[1:1]
  • DIVIDE_BYPASS=[TRUE:1]
  • I_INVERT=[FALSE:1]
 DCM
  • PSCLK=[PSCLK_INV:1] [PSCLK:0]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:0] [PSINCDEC_INV:1]
  • RST=[RST:1] [RST_INV:0]
 DCM_DCM
  • CLKDV_DIVIDE=[2:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[7:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • FACTORY_JF1=[0XC0:1]
  • FACTORY_JF2=[0X80:1]
  • PSCLK=[PSCLK_INV:1] [PSCLK:0]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:0] [PSINCDEC_INV:1]
  • RST=[RST:1] [RST_INV:0]
 DSP48A1
  • CEA=[CEA_INV:0] [CEA:1]
  • CEB=[CEB_INV:0] [CEB:1]
  • CEC=[CEC:1] [CEC_INV:0]
  • CECARRYIN=[CECARRYIN_INV:0] [CECARRYIN:1]
  • CED=[CED_INV:0] [CED:1]
  • CEM=[CEM_INV:0] [CEM:1]
  • CEOPMODE=[CEOPMODE_INV:0] [CEOPMODE:1]
  • CEP=[CEP:1] [CEP_INV:0]
  • CLK=[CLK:1] [CLK_INV:0]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTB=[RSTB:1] [RSTB_INV:0]
  • RSTC=[RSTC_INV:0] [RSTC:1]
  • RSTCARRYIN=[RSTCARRYIN_INV:0] [RSTCARRYIN:1]
  • RSTD=[RSTD_INV:0] [RSTD:1]
  • RSTM=[RSTM:1] [RSTM_INV:0]
  • RSTOPMODE=[RSTOPMODE_INV:0] [RSTOPMODE:1]
  • RSTP=[RSTP_INV:0] [RSTP:1]
 DSP48A1_DSP48A1
  • A0REG=[0:1]
  • A1REG=[0:1]
  • B0REG=[1:1]
  • B1REG=[0:1]
  • B_INPUT=[DIRECT:1]
  • CARRYINREG=[0:1]
  • CARRYINSEL=[OPMODE5:1]
  • CARRYOUTREG=[0:1]
  • CEA=[CEA_INV:0] [CEA:1]
  • CEB=[CEB_INV:0] [CEB:1]
  • CEC=[CEC:1] [CEC_INV:0]
  • CECARRYIN=[CECARRYIN_INV:0] [CECARRYIN:1]
  • CED=[CED_INV:0] [CED:1]
  • CEM=[CEM_INV:0] [CEM:1]
  • CEOPMODE=[CEOPMODE_INV:0] [CEOPMODE:1]
  • CEP=[CEP:1] [CEP_INV:0]
  • CLK=[CLK:1] [CLK_INV:0]
  • CREG=[0:1]
  • DREG=[0:1]
  • MREG=[0:1]
  • OPMODEREG=[0:1]
  • PREG=[0:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTB=[RSTB:1] [RSTB_INV:0]
  • RSTC=[RSTC_INV:0] [RSTC:1]
  • RSTCARRYIN=[RSTCARRYIN_INV:0] [RSTCARRYIN:1]
  • RSTD=[RSTD_INV:0] [RSTD:1]
  • RSTM=[RSTM:1] [RSTM_INV:0]
  • RSTOPMODE=[RSTOPMODE_INV:0] [RSTOPMODE:1]
  • RSTP=[RSTP_INV:0] [RSTP:1]
  • RSTTYPE=[SYNC:1]
 FF_SR
  • CK=[CK:29] [CK_INV:0]
  • SRINIT=[SRINIT0:28] [SRINIT1:1]
  • SYNC_ATTR=[ASYNC:27] [SYNC:2]
 IOB
  • O1=[O1_INV:0] [O1:2]
  • T1=[T1_INV:0] [T1:1]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:2]
  • TRI=[TRI_INV:0] [TRI:1]
 IOB_PAD
  • DRIVEATTRBOX=[12:2]
  • IOATTRBOX=[LVCMOS33:4]
  • SLEW=[SLOW:2]
 REG_SR
  • CK=[CK:139] [CK_INV:0]
  • LATCH_OR_FF=[FF:139]
  • SRINIT=[SRINIT0:138] [SRINIT1:1]
  • SYNC_ATTR=[ASYNC:97] [SYNC:42]
 SLICEL
  • BX=[BX_INV:0] [BX:149]
  • BY=[BY:22] [BY_INV:1]
  • CE=[CE:54] [CE_INV:8]
  • CIN=[CIN_INV:0] [CIN:64]
  • CLK=[CLK:139] [CLK_INV:0]
  • SR=[SR:53] [SR_INV:0]
 SLICEL_CYMUXF
  • 0=[0:76] [0_INV:0]
  • 1=[1_INV:0] [1:76]
 SLICEL_CYMUXG
  • 0=[0:69] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:134] [S0_INV:0]
 SLICEL_F6MUX
  • S0=[S0:5] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:44] [CE_INV:8]
  • CK=[CK:103] [CK_INV:0]
  • D=[D:103] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:103]
  • FFX_SR_ATTR=[SRLOW:96] [SRHIGH:7]
  • LATCH_OR_FF=[FF:103]
  • REV=[REV_INV:0] [REV:1]
  • SR=[SR:36] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:67] [SYNC:36]
 SLICEL_FFY
  • CE=[CE:46] [CE_INV:8]
  • CK=[CK:111] [CK_INV:0]
  • D=[D:110] [D_INV:1]
  • FFY_INIT_ATTR=[INIT0:109] [INIT1:2]
  • FFY_SR_ATTR=[SRLOW:95] [SRHIGH:16]
  • LATCH_OR_FF=[FF:111]
  • SR=[SR:44] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:67] [SYNC:44]
 SLICEL_XORF
  • 1=[1_INV:0] [1:50]
 SLICEX
  • CLK=[CLK:34] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=2
  • O=2
 BUFGMUX
  • I0=1
  • O=1
  • S=1
 BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
 BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
 BUFG_BUFG
  • I0=2
  • O=2
 BUFIO2
  • DIVCLK=1
  • I=1
 BUFIO2FB
  • I=1
  • O=1
 BUFIO2FB_BUFIO2FB
  • I=1
  • O=1
 BUFIO2_BUFIO2
  • DIVCLK=1
  • I=1
 CARRY4
  • CIN=57
  • CO0=3
  • CO3=57
  • CYINIT=20
  • DI0=73
  • DI1=67
  • DI2=62
  • DI3=57
  • O0=71
  • O1=67
  • O2=64
  • O3=59
  • S0=77
  • S1=70
  • S2=67
  • S3=62
 DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
 DCM_DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
 DSP48A1
  • A0=1
  • A1=1
  • A10=1
  • A11=1
  • A12=1
  • A13=1
  • A14=1
  • A15=1
  • A16=1
  • A17=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • A6=1
  • A7=1
  • A8=1
  • A9=1
  • B0=1
  • B1=1
  • B10=1
  • B11=1
  • B12=1
  • B13=1
  • B14=1
  • B15=1
  • B16=1
  • B17=1
  • B2=1
  • B3=1
  • B4=1
  • B5=1
  • B6=1
  • B7=1
  • B8=1
  • B9=1
  • C0=1
  • C1=1
  • C10=1
  • C11=1
  • C12=1
  • C13=1
  • C14=1
  • C15=1
  • C16=1
  • C17=1
  • C18=1
  • C19=1
  • C2=1
  • C20=1
  • C21=1
  • C22=1
  • C23=1
  • C24=1
  • C25=1
  • C26=1
  • C27=1
  • C28=1
  • C29=1
  • C3=1
  • C30=1
  • C31=1
  • C32=1
  • C33=1
  • C34=1
  • C35=1
  • C36=1
  • C37=1
  • C38=1
  • C39=1
  • C4=1
  • C40=1
  • C41=1
  • C42=1
  • C43=1
  • C44=1
  • C45=1
  • C46=1
  • C47=1
  • C5=1
  • C6=1
  • C7=1
  • C8=1
  • C9=1
  • CEA=1
  • CEB=1
  • CEC=1
  • CECARRYIN=1
  • CED=1
  • CEM=1
  • CEOPMODE=1
  • CEP=1
  • CLK=1
  • D0=1
  • D1=1
  • D10=1
  • D11=1
  • D12=1
  • D13=1
  • D14=1
  • D15=1
  • D16=1
  • D17=1
  • D2=1
  • D3=1
  • D4=1
  • D5=1
  • D6=1
  • D7=1
  • D8=1
  • D9=1
  • M10=1
  • M11=1
  • M12=1
  • M13=1
  • M14=1
  • M15=1
  • M16=1
  • M17=1
  • M18=1
  • M19=1
  • M20=1
  • M21=1
  • M22=1
  • M23=1
  • M24=1
  • M25=1
  • M3=1
  • M4=1
  • M5=1
  • M6=1
  • M7=1
  • M8=1
  • M9=1
  • OPMODE0=1
  • OPMODE1=1
  • OPMODE2=1
  • OPMODE3=1
  • OPMODE4=1
  • OPMODE5=1
  • OPMODE6=1
  • OPMODE7=1
  • RSTA=1
  • RSTB=1
  • RSTC=1
  • RSTCARRYIN=1
  • RSTD=1
  • RSTM=1
  • RSTOPMODE=1
  • RSTP=1
 DSP48A1_DSP48A1
  • A0=1
  • A1=1
  • A10=1
  • A11=1
  • A12=1
  • A13=1
  • A14=1
  • A15=1
  • A16=1
  • A17=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • A6=1
  • A7=1
  • A8=1
  • A9=1
  • B0=1
  • B1=1
  • B10=1
  • B11=1
  • B12=1
  • B13=1
  • B14=1
  • B15=1
  • B16=1
  • B17=1
  • B2=1
  • B3=1
  • B4=1
  • B5=1
  • B6=1
  • B7=1
  • B8=1
  • B9=1
  • C0=1
  • C1=1
  • C10=1
  • C11=1
  • C12=1
  • C13=1
  • C14=1
  • C15=1
  • C16=1
  • C17=1
  • C18=1
  • C19=1
  • C2=1
  • C20=1
  • C21=1
  • C22=1
  • C23=1
  • C24=1
  • C25=1
  • C26=1
  • C27=1
  • C28=1
  • C29=1
  • C3=1
  • C30=1
  • C31=1
  • C32=1
  • C33=1
  • C34=1
  • C35=1
  • C36=1
  • C37=1
  • C38=1
  • C39=1
  • C4=1
  • C40=1
  • C41=1
  • C42=1
  • C43=1
  • C44=1
  • C45=1
  • C46=1
  • C47=1
  • C5=1
  • C6=1
  • C7=1
  • C8=1
  • C9=1
  • CEA=1
  • CEB=1
  • CEC=1
  • CECARRYIN=1
  • CED=1
  • CEM=1
  • CEOPMODE=1
  • CEP=1
  • CLK=1
  • D0=1
  • D1=1
  • D10=1
  • D11=1
  • D12=1
  • D13=1
  • D14=1
  • D15=1
  • D16=1
  • D17=1
  • D2=1
  • D3=1
  • D4=1
  • D5=1
  • D6=1
  • D7=1
  • D8=1
  • D9=1
  • M10=1
  • M11=1
  • M12=1
  • M13=1
  • M14=1
  • M15=1
  • M16=1
  • M17=1
  • M18=1
  • M19=1
  • M20=1
  • M21=1
  • M22=1
  • M23=1
  • M24=1
  • M25=1
  • M3=1
  • M4=1
  • M5=1
  • M6=1
  • M7=1
  • M8=1
  • M9=1
  • OPMODE0=1
  • OPMODE1=1
  • OPMODE2=1
  • OPMODE3=1
  • OPMODE4=1
  • OPMODE5=1
  • OPMODE6=1
  • OPMODE7=1
  • RSTA=1
  • RSTB=1
  • RSTC=1
  • RSTCARRYIN=1
  • RSTD=1
  • RSTM=1
  • RSTOPMODE=1
  • RSTP=1
 FF_SR
  • CE=18
  • CK=29
  • D=29
  • Q=29
  • SR=2
 HARD0
  • 0=16
 HARD1
  • 1=3
 IOB
  • I=3
  • O1=2
  • PAD=4
  • T1=1
 IOB_IMUX
  • I=3
  • OUT=3
 IOB_INBUF
  • IN=3
  • OUT=3
 IOB_OUTBUF
  • IN=2
  • OUT=2
  • TRI=1
 IOB_PAD
  • PAD=4
 LUT5
  • A1=30
  • A2=42
  • A3=80
  • A4=64
  • A5=76
  • O5=199
 LUT6
  • A1=922
  • A2=1261
  • A3=1380
  • A4=1542
  • A5=1565
  • A6=1619
  • O6=1629
 MULT18X18
  • A0=1
  • A1=1
  • A10=1
  • A11=1
  • A12=1
  • A13=1
  • A14=1
  • A15=1
  • A16=1
  • A17=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • A6=1
  • A7=1
  • A8=1
  • A9=1
  • B0=1
  • B1=1
  • B10=1
  • B11=1
  • B12=1
  • B13=1
  • B14=1
  • B15=1
  • B16=1
  • B17=1
  • B2=1
  • B3=1
  • B4=1
  • B5=1
  • B6=1
  • B7=1
  • B8=1
  • B9=1
  • P10=1
  • P11=1
  • P12=1
  • P13=1
  • P14=1
  • P15=1
  • P16=1
  • P17=1
  • P18=1
  • P19=1
  • P20=1
  • P21=1
  • P22=1
  • P23=1
  • P24=1
  • P25=1
 MULT18X18_BLACKBOX
  • A0=1
  • A1=1
  • A10=1
  • A11=1
  • A12=1
  • A13=1
  • A14=1
  • A15=1
  • A16=1
  • A17=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • A6=1
  • A7=1
  • A8=1
  • A9=1
  • B0=1
  • B1=1
  • B10=1
  • B11=1
  • B12=1
  • B13=1
  • B14=1
  • B15=1
  • B16=1
  • B17=1
  • B2=1
  • B3=1
  • B4=1
  • B5=1
  • B6=1
  • B7=1
  • B8=1
  • B9=1
  • P10=1
  • P11=1
  • P12=1
  • P13=1
  • P14=1
  • P15=1
  • P16=1
  • P17=1
  • P18=1
  • P19=1
  • P20=1
  • P21=1
  • P22=1
  • P23=1
  • P24=1
  • P25=1
 PAD
  • PAD=4
 REG_SR
  • CE=112
  • CK=139
  • D=139
  • Q=139
  • SR=42
 SELMUX2_1
  • 0=58
  • 1=58
  • OUT=58
  • S0=58
 SLICEL
  • BX=149
  • BY=23
  • CE=62
  • CIN=64
  • CLK=139
  • COUT=69
  • F1=360
  • F2=295
  • F3=277
  • F4=231
  • F5=10
  • FXINA=5
  • FXINB=5
  • G1=352
  • G2=299
  • G3=258
  • G4=199
  • SR=53
  • X=226
  • XB=2
  • XQ=103
  • Y=107
  • YQ=111
 SLICEL_C1VDD
  • 1=14
 SLICEL_C2VDD
  • 1=14
 SLICEL_CYMUXF
  • 0=76
  • 1=76
  • OUT=76
  • S0=76
 SLICEL_CYMUXG
  • 0=69
  • 1=69
  • OUT=69
  • S0=69
 SLICEL_F
  • A1=360
  • A2=295
  • A3=277
  • A4=231
  • D=362
 SLICEL_F5MUX
  • F=134
  • G=134
  • OUT=134
  • S0=134
 SLICEL_F6MUX
  • 0=5
  • 1=5
  • OUT=5
  • S0=5
 SLICEL_FFX
  • CE=52
  • CK=103
  • D=103
  • Q=103
  • REV=1
  • SR=36
 SLICEL_FFY
  • CE=54
  • CK=111
  • D=111
  • Q=111
  • SR=44
 SLICEL_G
  • A1=352
  • A2=299
  • A3=258
  • A4=199
  • D=353
 SLICEL_GNDF
  • 0=62
 SLICEL_GNDG
  • 0=55
 SLICEL_XORF
  • 0=50
  • 1=50
  • O=50
 SLICEL_XORG
  • 0=49
  • 1=49
  • O=49
 SLICEX
  • A=297
  • A1=177
  • A2=242
  • A3=273
  • A4=291
  • A5=312
  • A6=313
  • AMUX=17
  • AQ=23
  • AX=4
  • B=268
  • B1=166
  • B2=239
  • B3=266
  • B4=277
  • B5=282
  • B6=282
  • BMUX=19
  • BQ=21
  • BX=6
  • C=258
  • C1=148
  • C2=213
  • C3=243
  • C4=257
  • C5=271
  • C6=271
  • CE=24
  • CLK=34
  • CMUX=17
  • CQ=20
  • CX=4
  • D=252
  • D1=137
  • D2=209
  • D3=238
  • D4=255
  • D5=262
  • D6=262
  • DMUX=18
  • DQ=16
  • DX=5
  • SR=2
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s200-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s200-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
Start 0 0 0 0 0 0 0
_impact 98 76 0 0 0 0 0
arwz 5 5 0 0 0 0 0
bitgen 751 746 0 0 0 0 0
edif2ngd 1 1 0 0 0 0 0
map 900 767 0 0 0 0 0
netgen 9 9 0 0 0 0 0
ngc2edif 3 3 0 0 0 0 0
ngcbuild 9 9 0 0 0 0 0
ngdbuild 968 957 0 0 0 0 0
obngc 9 9 0 0 0 0 0
par 764 759 3 0 0 0 0
trce 736 736 0 0 0 0 0
xst 1423 1315 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/pn_db_nsw_select_ip.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Constraints Editor PROP_intProjectCreationTimestamp=2015-02-11T10:00:54
PROP_intWbtProjectID=24F03BEC37754E5D93498E51C9A3D99B PROP_intWbtProjectIteration=13
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=false PROP_DevFamily=Spartan3
PROP_DevDevice=xc3s200 PROP_DevFamilyPMName=spartan3
PROP_DevPackage=tq144 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=4
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_DCM=1 NGDBUILD_NUM_FD=91 NGDBUILD_NUM_FDE=43
NGDBUILD_NUM_FDR=1 NGDBUILD_NUM_FDRE=55 NGDBUILD_NUM_FDRS=1 NGDBUILD_NUM_FDS=15
NGDBUILD_NUM_FDSE=8 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=15
NGDBUILD_NUM_IOBUF=1 NGDBUILD_NUM_LUT1=104 NGDBUILD_NUM_LUT2=54 NGDBUILD_NUM_LUT2_L=1
NGDBUILD_NUM_LUT3=96 NGDBUILD_NUM_LUT3_D=11 NGDBUILD_NUM_LUT3_L=2 NGDBUILD_NUM_LUT4=403
NGDBUILD_NUM_LUT4_D=21 NGDBUILD_NUM_LUT4_L=6 NGDBUILD_NUM_MULT18X18=1 NGDBUILD_NUM_MUXCY=145
NGDBUILD_NUM_MUXF5=134 NGDBUILD_NUM_MUXF6=5 NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=99
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_DCM=1 NGDBUILD_NUM_FD=91 NGDBUILD_NUM_FDE=43
NGDBUILD_NUM_FDR=1 NGDBUILD_NUM_FDRE=55 NGDBUILD_NUM_FDRS=1 NGDBUILD_NUM_FDS=15
NGDBUILD_NUM_FDSE=8 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=15 NGDBUILD_NUM_LUT1=104 NGDBUILD_NUM_LUT2=54 NGDBUILD_NUM_LUT2_L=1
NGDBUILD_NUM_LUT3=96 NGDBUILD_NUM_LUT3_D=11 NGDBUILD_NUM_LUT3_L=2 NGDBUILD_NUM_LUT4=403
NGDBUILD_NUM_LUT4_D=21 NGDBUILD_NUM_LUT4_L=6 NGDBUILD_NUM_MULT18X18=1 NGDBUILD_NUM_MUXCY=145
NGDBUILD_NUM_MUXF5=134 NGDBUILD_NUM_MUXF6=5 NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_OBUFT=1
NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=99
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s200-4-tq144 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=8
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5