top Project Status (04/18/2015 - 09:34:51)
Project File:	Thermisotor_DS18B20.xise	Parser Errors:	No Errors
Module Name:	top	Implementation State:	Programming File Generated
Target Device:	xc3s200-4tq144	Errors:
Product Version:	ISE 14.2	Warnings:
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	X 1 Failing Constraint
Environment:	System Settings	Final Timing Score:	85772  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	214	3,840	5%
Number of 4 input LUTs	610	3,840	15%
Number of occupied Slices	396	1,920	20%
Number of Slices containing only related logic	396	396	100%
Number of Slices containing unrelated logic	0	396	0%
Total Number of 4 input LUTs	715	3,840	18%
Number used as logic	610
Number used as a route-thru	105
Number of bonded IOBs	4	97	4%
Number of MULT18X18s	1	12	8%
Number of BUFGMUXs	1	8	12%
Number of DCMs	1	4	25%
Average Fanout of Non-Clock Nets	4.17

 

Performance Summary				[-]
Final Timing Score:	85772 (Setup: 85772, Hold: 0, Component Switching Limit: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	X 1 Failing Constraint

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Åä 4 18 09:33:58 2015	0	21 Warnings (16 new)	3 Infos (1 new)
Translation Report	Current	Åä 4 18 09:34:03 2015	0	0	1 Info (1 new)
Map Report	Current	Åä 4 18 09:34:07 2015
Place and Route Report	Current	Åä 4 18 09:34:37 2015	0	4 Warnings (0 new)	0
Power Report
Post-PAR Static Timing Report	Current	Åä 4 18 09:34:40 2015	0	0	5 Infos (2 new)
Bitgen Report	Current	Åä 4 18 09:34:45 2015	0	0	2 Infos (2 new)

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	Åä 4 18 09:34:45 2015
WebTalk Log File	Current	Åä 4 18 09:34:51 2015

Date Generated: 04/18/2015 - 09:34:51