| LCD Project Status | |||
| Project File: | TextLCD_16by2.xise | Parser Errors: | No Errors |
| Module Name: | LCD | Implementation State: | Synthesized |
| Target Device: | xc3s200-4tq144 |
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No Errors |
| Product Version: | ISE 14.2 |
|
9 Warnings (0 new) |
| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slices | 54 | 1920 | 2% | |
| Number of Slice Flip Flops | 31 | 3840 | 0% | |
| Number of 4 input LUTs | 98 | 3840 | 2% | |
| Number of bonded IOBs | 11 | 97 | 11% | |
| Number of GCLKs | 1 | 8 | 12% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | 配 4 18 11:35:29 2015 | 0 | 9 Warnings (0 new) | 0 | |
| Translation Report | Out of Date | 格 4 16 16:26:23 2015 | 0 | 0 | 0 | |
| Map Report | Out of Date | 格 4 16 16:26:26 2015 | 0 | 0 | 2 Infos (0 new) | |
| Place and Route Report | Out of Date | 格 4 16 16:26:31 2015 | 0 | 0 | 2 Infos (1 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Out of Date | 格 4 16 16:26:34 2015 | 0 | 0 | 6 Infos (2 new) | |
| Bitgen Report | Out of Date | 格 4 16 16:26:37 2015 | 0 | 0 | 1 Info (1 new) | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| WebTalk Report | Out of Date | 格 4 16 16:26:38 2015 | |
| WebTalk Log File | Out of Date | 格 4 16 16:26:43 2015 | |