Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.2 (WebPack) - P.28xd Target Family: Spartan3
OS Platform: NT64 Target Device: xc3s200
Project ID (random number) ea081235f4e2469da4cf3e33d5a71d61.AA1CB9A9886F4D6AB3350CD8809573A8.5 Target Package: tq144
Registration ID __0_0_0 Target Speed: -4
Date Generated 2015-04-18T10:41:18 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i5-4670 CPU @ 3.40GHz CPU Speed 3392 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=1
  • 28-bit comparator greater=1
 Counters=3
  • 17-bit up counter=1
  • 2-bit up counter=1
  • 28-bit up counter=1
 Registers=3
  • Flip-Flops=3
 		MiscellaneousStatistics
  • AGG_BONDED_IO=3
  • AGG_IO=3
  • AGG_SLICE=42
  • NUM_4_INPUT_LUT=75
  • NUM_BONDED_IOB=3
  • NUM_BUFGMUX=1
  • NUM_CYMUX=68
  • NUM_LUT_RT=47
  • NUM_SLICEL=42
  • NUM_SLICE_FF=50
  • NUM_XOR=45
 		NetStatistics
  • NumNets_Active=93
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=27
  • NumNodesOfType_Active_CNTRLPIN=52
  • NumNodesOfType_Active_DOUBLE=161
  • NumNodesOfType_Active_DUMMY=129
  • NumNodesOfType_Active_DUMMYESC=1
  • NumNodesOfType_Active_GLOBAL=11
  • NumNodesOfType_Active_HUNIHEX=1
  • NumNodesOfType_Active_INPUT=165
  • NumNodesOfType_Active_IOBOUTPUT=1
  • NumNodesOfType_Active_OMUX=91
  • NumNodesOfType_Active_OUTPUT=89
  • NumNodesOfType_Active_PREBXBY=2
  • NumNodesOfType_Active_VFULLHEX=5
  • NumNodesOfType_Active_VUNIHEX=8
  • NumNodesOfType_Gnd_DOUBLE=1
  • NumNodesOfType_Gnd_INPUT=3
  • NumNodesOfType_Gnd_OMUX=2
  • NumNodesOfType_Gnd_OUTPUT=3
  • NumNodesOfType_Gnd_PREBXBY=3
 SiteStatistics
  • IOB-DIFFM=2
  • IOB-DIFFS=1
  • SLICEL-SLICEM=19
 		SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IOB=3
  • IOB_INBUF=1
  • IOB_OUTBUF=2
  • IOB_PAD=3
  • SLICEL=42
  • SLICEL_C1VDD=4
  • SLICEL_C2VDD=4
  • SLICEL_CYMUXF=36
  • SLICEL_CYMUXG=32
  • SLICEL_F=39
  • SLICEL_FFX=24
  • SLICEL_FFY=26
  • SLICEL_G=36
  • SLICEL_GNDF=32
  • SLICEL_GNDG=28
  • SLICEL_XORF=23
  • SLICEL_XORG=22
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
 FF_SR
  • CK=[CK:1] [CK_INV:0]
  • SRINIT=[SRINIT1:1]
  • SYNC_ATTR=[ASYNC:1]
 IOB
  • O1=[O1_INV:0] [O1:2]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:2]
 IOB_PAD
  • DRIVEATTRBOX=[12:2]
  • IOATTRBOX=[LVCMOS33:3]
  • SLEW=[SLOW:2]
 REG_SR
  • CK=[CK:50] [CK_INV:0]
  • LATCH_OR_FF=[FF:50]
  • SRINIT=[SRINIT0:49] [SRINIT1:1]
  • SYNC_ATTR=[ASYNC:50]
 SLICEL
  • BX=[BX_INV:0] [BX:5]
  • BY=[BY:1] [BY_INV:2]
  • CE=[CE:4] [CE_INV:23]
  • CIN=[CIN_INV:0] [CIN:32]
  • CLK=[CLK:27] [CLK_INV:0]
  • SR=[SR:25] [SR_INV:0]
 SLICEL_CYMUXF
  • 0=[0:36] [0_INV:0]
  • 1=[1_INV:0] [1:36]
 SLICEL_CYMUXG
  • 0=[0:32] [0_INV:0]
 SLICEL_FFX
  • CE=[CE:1] [CE_INV:23]
  • CK=[CK:24] [CK_INV:0]
  • D=[D:24] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:24]
  • FFX_SR_ATTR=[SRLOW:24]
  • LATCH_OR_FF=[FF:24]
  • SR=[SR:23] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:1] [SYNC:23]
 SLICEL_FFY
  • CE=[CE:4] [CE_INV:22]
  • CK=[CK:26] [CK_INV:0]
  • D=[D:24] [D_INV:2]
  • FFY_INIT_ATTR=[INIT0:25] [INIT1:1]
  • FFY_SR_ATTR=[SRLOW:26]
  • LATCH_OR_FF=[FF:26]
  • SR=[SR:24] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:2] [SYNC:24]
 SLICEL_XORF
  • 1=[1_INV:0] [1:23]
 SLICEX
  • CLK=[CLK:16] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
 BUFGMUX
  • I0=1
  • O=1
  • S=1
 BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
 BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
 BUFG_BUFG
  • I0=1
  • O=1
 CARRY4
  • CIN=11
  • CO1=1
  • CO3=11
  • CYINIT=3
  • DI0=13
  • DI1=13
  • DI2=12
  • DI3=11
  • O0=12
  • O1=11
  • O2=11
  • O3=11
  • S0=14
  • S1=13
  • S2=12
  • S3=12
 FF_SR
  • CK=1
  • D=1
  • Q=1
 HARD0
  • 0=2
 HARD1
  • 1=1
 IOB
  • I=1
  • O1=2
  • PAD=3
 IOB_IMUX
  • I=1
  • OUT=1
 IOB_INBUF
  • IN=1
  • OUT=1
 IOB_OUTBUF
  • IN=2
  • OUT=2
 IOB_PAD
  • PAD=3
 LUT5
  • A1=6
  • A2=2
  • A3=4
  • A4=3
  • A5=3
  • O5=51
 LUT6
  • A1=16
  • A2=18
  • A3=64
  • A4=67
  • A5=109
  • A6=112
  • O6=113
 PAD
  • PAD=3
 REG_SR
  • CE=2
  • CK=50
  • D=50
  • Q=50
 SLICEL
  • BX=5
  • BY=3
  • CE=27
  • CIN=32
  • CLK=27
  • COUT=32
  • F1=39
  • F2=10
  • F3=8
  • F4=8
  • G1=36
  • G2=11
  • G3=8
  • G4=8
  • SR=25
  • X=1
  • XB=3
  • XQ=24
  • Y=2
  • YQ=26
 SLICEL_C1VDD
  • 1=4
 SLICEL_C2VDD
  • 1=4
 SLICEL_CYMUXF
  • 0=36
  • 1=36
  • OUT=36
  • S0=36
 SLICEL_CYMUXG
  • 0=32
  • 1=32
  • OUT=32
  • S0=32
 SLICEL_F
  • A1=39
  • A2=10
  • A3=8
  • A4=8
  • D=39
 SLICEL_FFX
  • CE=24
  • CK=24
  • D=24
  • Q=24
  • SR=23
 SLICEL_FFY
  • CE=26
  • CK=26
  • D=26
  • Q=26
  • SR=24
 SLICEL_G
  • A1=36
  • A2=11
  • A3=8
  • A4=8
  • D=36
 SLICEL_GNDF
  • 0=32
 SLICEL_GNDG
  • 0=28
 SLICEL_XORF
  • 0=23
  • 1=23
  • O=23
 SLICEL_XORG
  • 0=22
  • 1=22
  • O=22
 SLICEX
  • A=4
  • A1=7
  • A2=7
  • A3=17
  • A4=18
  • A5=17
  • A6=17
  • AMUX=1
  • AQ=15
  • AX=1
  • B=2
  • B1=2
  • B2=3
  • B3=15
  • B4=16
  • B5=15
  • B6=16
  • BMUX=1
  • BQ=14
  • C=4
  • C1=3
  • C2=3
  • C3=14
  • C4=15
  • C5=15
  • C6=15
  • CE=1
  • CLK=16
  • CQ=11
  • D=3
  • D1=1
  • D2=1
  • D3=12
  • D4=12
  • D5=13
  • D6=13
  • DQ=10
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s200-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s200-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s200-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s200-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
Start 0 0 0 0 0 0 0
_impact 98 76 0 0 0 0 0
arwz 5 5 0 0 0 0 0
bitgen 753 748 0 0 0 0 0
edif2ngd 1 1 0 0 0 0 0
map 902 769 0 0 0 0 0
netgen 9 9 0 0 0 0 0
ngc2edif 3 3 0 0 0 0 0
ngcbuild 9 9 0 0 0 0 0
ngdbuild 970 959 0 0 0 0 0
obngc 9 9 0 0 0 0 0
par 766 761 3 0 0 0 0
trce 738 738 0 0 0 0 0
xst 1428 1320 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/pn_db_nsw_select_ip.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/top PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Constraints Editor
PROP_intProjectCreationTimestamp=2015-02-04T17:38:49 PROP_intWbtProjectID=AA1CB9A9886F4D6AB3350CD8809573A8
PROP_intWbtProjectIteration=5 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_selectedSimRootSourceNode_behav=work.top PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=true PROP_DevFamily=Spartan3
PROP_DevDevice=xc3s200 PROP_DevFamilyPMName=spartan3
PROP_DevPackage=tq144 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDE=3 NGDBUILD_NUM_FDRE=47 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_INV=10 NGDBUILD_NUM_LUT1=47 NGDBUILD_NUM_LUT2=5 NGDBUILD_NUM_LUT4=16
NGDBUILD_NUM_MUXCY=68 NGDBUILD_NUM_OBUF=2 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=45
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDE=3 NGDBUILD_NUM_FDRE=47 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=10 NGDBUILD_NUM_LUT1=47 NGDBUILD_NUM_LUT2=5
NGDBUILD_NUM_LUT4=16 NGDBUILD_NUM_MUXCY=68 NGDBUILD_NUM_OBUF=2 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=45
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s200-4-tq144 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=8
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5