top Project Status (04/18/2015 - 13:47:02)
Project File: SR04.xise Parser Errors: No Errors
Module Name: top Implementation State: Programming File Generated
Target Device: xc3s200-4tq144
  • Errors:
No Errors
Product Version:ISE 14.2
  • Warnings:
22 Warnings (2 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 216 3,840 5%  
Number of 4 input LUTs 903 3,840 23%  
Number of occupied Slices 603 1,920 31%  
    Number of Slices containing only related logic 603 603 100%  
    Number of Slices containing unrelated logic 0 603 0%  
Total Number of 4 input LUTs 1,074 3,840 27%  
    Number used as logic 903      
    Number used as a route-thru 171      
Number of bonded IOBs 13 97 13%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 3.39      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentÅä 4 18 13:46:34 2015022 Warnings (2 new)1 Info (0 new)
Translation ReportCurrentÅä 4 18 13:46:39 2015000
Map ReportCurrentÅä 4 18 13:46:43 2015002 Infos (0 new)
Place and Route ReportCurrentÅä 4 18 13:46:49 2015000
Power Report     
Post-PAR Static Timing ReportCurrentÅä 4 18 13:46:52 2015005 Infos (2 new)
Bitgen ReportCurrentÅä 4 18 13:46:56 2015001 Info (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateÅä 4 18 13:46:57 2015
WebTalk Log FileOut of DateÅä 4 18 13:47:02 2015

Date Generated: 04/18/2015 - 13:48:47