top Project Status (04/18/2015 - 11:08:15)
Project File: RealTimeClock1307.xise Parser Errors: No Errors
Module Name: top Implementation State: Programming File Generated
Target Device: xc3s200-4tq144
  • Errors:
No Errors
Product Version:ISE 14.2
  • Warnings:
43 Warnings (3 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 266 3,840 6%  
Number of 4 input LUTs 693 3,840 18%  
Number of occupied Slices 422 1,920 21%  
    Number of Slices containing only related logic 422 422 100%  
    Number of Slices containing unrelated logic 0 422 0%  
Total Number of 4 input LUTs 795 3,840 20%  
    Number used as logic 693      
    Number used as a route-thru 102      
Number of bonded IOBs 13 97 13%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 3.31      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentÅä 4 18 13:33:38 2015040 Warnings (3 new)2 Infos (0 new)
Translation ReportCurrentÅä 4 18 13:33:42 2015000
Map ReportCurrentÅä 4 18 13:33:46 201503 Warnings (0 new)2 Infos (0 new)
Place and Route ReportCurrentÅä 4 18 13:33:51 2015000
Power Report     
Post-PAR Static Timing ReportCurrentÅä 4 18 13:33:54 2015005 Infos (0 new)
Bitgen ReportCurrentÅä 4 18 13:33:58 2015001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentÅä 4 18 13:33:58 2015
WebTalk Log FileCurrentÅä 4 18 13:34:04 2015

Date Generated: 04/18/2015 - 13:35:00