top Project Status (04/18/2015 - 14:16:01)
Project File:	RS485.xise	Parser Errors:	No Errors
Module Name:	top	Implementation State:	Programming File Generated
Target Device:	xc3s200-4tq144	Errors:	No Errors
Product Version:	ISE 14.2	Warnings:	18 Warnings (18 new)
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	84	3,840	2%
Number of 4 input LUTs	97	3,840	2%
Number of occupied Slices	72	1,920	3%
Number of Slices containing only related logic	72	72	100%
Number of Slices containing unrelated logic	0	72	0%
Total Number of 4 input LUTs	134	3,840	3%
Number used as logic	97
Number used as a route-thru	37
Number of bonded IOBs	4	97	4%
Number of BUFGMUXs	1	8	12%
Average Fanout of Non-Clock Nets	3.41

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0, Component Switching Limit: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Åä 4 18 14:15:36 2015	0	18 Warnings (18 new)	2 Infos (2 new)
Translation Report	Current	Åä 4 18 14:15:40 2015	0	0	0
Map Report	Current	Åä 4 18 14:15:44 2015	0	0	2 Infos (1 new)
Place and Route Report	Current	Åä 4 18 14:15:48 2015	0	0	0
Power Report
Post-PAR Static Timing Report	Current	Åä 4 18 14:15:51 2015	0	0	5 Infos (2 new)
Bitgen Report	Current	Åä 4 18 14:15:54 2015	0	0	1 Info (1 new)

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	Åä 4 18 14:15:54 2015
WebTalk Log File	Current	Åä 4 18 14:16:00 2015

Date Generated: 04/18/2015 - 14:16:01