Device Usage Statistics Report

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.

Software Version and Target Device
Product Version:	ISE:14.2 (WebPack) - P.28xd	Target Family:	Spartan3
OS Platform:	NT64	Target Device:	xc3s200
Project ID (random number)	ea081235f4e2469da4cf3e33d5a71d61.A26913821B0D4A4E8EA1AD2F2A4DCB4D.6	Target Package:	tq144
Registration ID	__0_0_0	Target Speed:	-4
Date Generated	2015-04-18T14:09:03	Tool Flow	ISE

User Environment
OS Name	Microsoft Windows 7 , 64-bit	OS Release	Service Pack 1 (build 7601)
CPU Name	Intel(R) Core(TM) i5-4670 CPU @ 3.40GHz	CPU Speed	3392 MHz

Device Usage Statistics
Macro Statistics	Miscellaneous Statistics	Net Statistics	Site Usage
Adders/Subtractors=6 12-bit adder=2 3-bit adder=1 4-bit adder=3 Comparators=4 4-bit comparator greatequal=1 4-bit comparator less=1 5-bit comparator greater=1 5-bit comparator lessequal=1 Counters=4 2-bit up counter=1 23-bit up counter=1 3-bit up counter=1 4-bit up counter=1 Multiplexers=1 8-bit 5-to-1 multiplexer=1 Registers=91 Flip-Flops=91	MiscellaneousStatistics AGG_BONDED_IO=3 AGG_IO=3 AGG_SLICE=114 NUM_4_INPUT_LUT=162 NUM_BONDED_IOB=3 NUM_BUFGMUX=1 NUM_CYMUX=50 NUM_LUT_RT=28 NUM_SLICEL=114 NUM_SLICE_FF=123 NUM_XOR=47	NetStatistics NumNets_Active=230 NumNets_Gnd=1 NumNets_Vcc=1 NumNodesOfType_Active_CLKPIN=68 NumNodesOfType_Active_CNTRLPIN=102 NumNodesOfType_Active_DOUBLE=404 NumNodesOfType_Active_DUMMY=476 NumNodesOfType_Active_DUMMYESC=2 NumNodesOfType_Active_GLOBAL=20 NumNodesOfType_Active_HUNIHEX=9 NumNodesOfType_Active_INPUT=560 NumNodesOfType_Active_IOBOUTPUT=2 NumNodesOfType_Active_OMUX=256 NumNodesOfType_Active_OUTPUT=226 NumNodesOfType_Active_PREBXBY=60 NumNodesOfType_Active_VFULLHEX=6 NumNodesOfType_Active_VUNIHEX=11 NumNodesOfType_Gnd_DOUBLE=1 NumNodesOfType_Gnd_INPUT=5 NumNodesOfType_Gnd_OMUX=5 NumNodesOfType_Gnd_OUTPUT=4 NumNodesOfType_Gnd_PREBXBY=5 SiteStatistics IOB-DIFFM=2 IOB-DIFFS=1 SLICEL-SLICEM=56	SiteSummary BUFGMUX=1 BUFGMUX_GCLKMUX=1 BUFGMUX_GCLK_BUFFER=1 IOB=3 IOB_INBUF=2 IOB_OUTBUF=1 IOB_PAD=3 SLICEL=114 SLICEL_C1VDD=3 SLICEL_CYMUXF=26 SLICEL_CYMUXG=24 SLICEL_F=83 SLICEL_F5MUX=9 SLICEL_FFX=60 SLICEL_FFY=63 SLICEL_G=79 SLICEL_GNDF=23 SLICEL_GNDG=24 SLICEL_XORF=24 SLICEL_XORG=23

Configuration Data
BUFGMUX S=[S_INV:1] [S:0] BUFGMUX_GCLKMUX DISABLE_ATTR=[LOW:1] S=[S_INV:1] [S:0] BUFIO2FB_BUFIO2FB DIVIDE_BYPASS=[TRUE:1] INVERT_INPUTS=[FALSE:1] BUFIO2_BUFIO2 DIVIDE=[1:1] DIVIDE_BYPASS=[TRUE:1] I_INVERT=[FALSE:1] DCM PSCLK=[PSCLK_INV:0] [PSCLK:1] PSEN=[PSEN_INV:0] [PSEN:1] PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0] RST=[RST:1] [RST_INV:0] DCM_DCM CLKDV_DIVIDE=[2.0:1] CLKIN_DIVIDE_BY_2=[FALSE:1] CLKOUT_PHASE_SHIFT=[NONE:1] CLK_FEEDBACK=[1X:1] DESKEW_ADJUST=[5:1] DFS_FREQUENCY_MODE=[LOW:1] DLL_FREQUENCY_MODE=[LOW:1] DSS_MODE=[NONE:1] DUTY_CYCLE_CORRECTION=[TRUE:1] PSCLK=[PSCLK_INV:0] [PSCLK:1] PSEN=[PSEN_INV:0] [PSEN:1] PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0] RST=[RST:1] [RST_INV:0] STARTUP_WAIT=[FALSE:1] VERY_HIGH_FREQUENCY=[FALSE:1]	FF_SR CK=[CK:1] [CK_INV:0] SRINIT=[SRINIT0:1] SYNC_ATTR=[SYNC:1] IOB O1=[O1_INV:0] [O1:1] IOB_OUTBUF IN=[IN_INV:0] [IN:1] IOB_PAD DRIVEATTRBOX=[12:1] IOATTRBOX=[LVCMOS33:3] SLEW=[SLOW:1] REG_SR CK=[CK:123] [CK_INV:0] LATCH_OR_FF=[FF:123] SRINIT=[SRINIT0:122] [SRINIT1:1] SYNC_ATTR=[ASYNC:103] [SYNC:20] SLICEL BX=[BX_INV:2] [BX:34] BY=[BY:29] [BY_INV:1] CE=[CE:68] [CE_INV:0] CIN=[CIN_INV:0] [CIN:23] CLK=[CLK:68] [CLK_INV:0] SR=[SR:34] [SR_INV:0]	SLICEL_CYMUXF 0=[0:26] [0_INV:0] 1=[1_INV:0] [1:26] SLICEL_CYMUXG 0=[0:24] [0_INV:0] SLICEL_F5MUX S0=[S0:9] [S0_INV:0] SLICEL_FFX CE=[CE:60] [CE_INV:0] CK=[CK:60] [CK_INV:0] D=[D:58] [D_INV:2] FFX_INIT_ATTR=[INIT0:60] FFX_SR_ATTR=[SRLOW:60] LATCH_OR_FF=[FF:60] REV=[REV_INV:0] [REV:1] SR=[SR:34] [SR_INV:0] SYNC_ATTR=[ASYNC:26] [SYNC:34] SLICEL_FFY CE=[CE:63] [CE_INV:0] CK=[CK:63] [CK_INV:0] D=[D:62] [D_INV:1] FFY_INIT_ATTR=[INIT0:62] [INIT1:1] FFY_SR_ATTR=[SRLOW:63] LATCH_OR_FF=[FF:63] SR=[SR:30] [SR_INV:0] SYNC_ATTR=[ASYNC:33] [SYNC:30]	SLICEL_XORF 1=[1_INV:0] [1:24] SLICEX CLK=[CLK:39] [CLK_INV:0]

Pin Data
BUFG I0=2 O=2 BUFGMUX I0=1 O=1 S=1 BUFGMUX_GCLKMUX I0=1 OUT=1 S=1 BUFGMUX_GCLK_BUFFER IN=1 OUT=1 BUFG_BUFG I0=2 O=2 BUFIO2 DIVCLK=1 I=1 BUFIO2FB I=1 O=1 BUFIO2FB_BUFIO2FB I=1 O=1 BUFIO2_BUFIO2 DIVCLK=1 I=1 CARRY4 CIN=9 CO3=9 CYINIT=3 DI0=12 DI1=12 DI2=11 DI3=9 O0=12 O1=12 O2=12 O3=11 S0=12 S1=12 S2=12 S3=11 DCM CLK0=1 CLKFB=1 CLKFX=1 CLKIN=1 PSCLK=1 PSEN=1 PSINCDEC=1 RST=1 DCM_DCM CLK0=1 CLKFB=1 CLKFX=1 CLKIN=1 PSCLK=1 PSEN=1 PSINCDEC=1 RST=1	FF_SR CK=1 D=1 Q=1 SR=1 HARD0 0=3 IOB I=2 O1=1 PAD=3 IOB_IMUX I=2 OUT=2 IOB_INBUF IN=2 OUT=2 IOB_OUTBUF IN=1 OUT=1 IOB_PAD PAD=3 LUT5 A1=2 A2=5 A3=7 A4=7 A5=6 O5=46 LUT6 A1=127 A2=158 A3=167 A4=179 A5=211 A6=217 O6=218 PAD PAD=3 REG_SR CE=67 CK=123 D=123 Q=123 SR=20 SELMUX2_1 0=1 1=1 OUT=1 S0=1 SLICEL BX=36 BY=30 CE=68 CIN=23 CLK=68 COUT=24 F1=83 F2=66 F3=59 F4=31 G1=79 G2=66 G3=59 G4=32 SR=34 X=44 XQ=60 Y=33 YQ=63	SLICEL_C1VDD 1=3 SLICEL_CYMUXF 0=26 1=26 OUT=26 S0=26 SLICEL_CYMUXG 0=24 1=24 OUT=24 S0=24 SLICEL_F A1=83 A2=66 A3=59 A4=31 D=83 SLICEL_F5MUX F=9 G=9 OUT=9 S0=9 SLICEL_FFX CE=60 CK=60 D=60 Q=60 REV=1 SR=34 SLICEL_FFY CE=63 CK=63 D=63 Q=63 SR=30 SLICEL_G A1=79 A2=66 A3=59 A4=32 D=79 SLICEL_GNDF 0=23 SLICEL_GNDG 0=24 SLICEL_XORF 0=24 1=24 O=24 SLICEL_XORG 0=23 1=23 O=23 SLICEX A=20 A1=37 A2=44 A3=48 A4=50 A5=51 A6=51 AMUX=1 AQ=33 AX=1 B=17 B1=30 B2=39 B3=42 B4=43 B5=42 B6=43 BMUX=3 BQ=26 C=10 C1=26 C2=35 C3=36 C4=36 C5=38 C6=38 CE=17 CLK=39 CMUX=2 CQ=29 D=12 D1=24 D2=33 D3=34 D4=34 D5=34 D6=34 DMUX=2 DQ=22 SR=6

Tool Usage

Command Line History

xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s200-tq144-4 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc3s200-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s200-tq144-4 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc3s200-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s200-tq144-4 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc3s200-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s200-tq144-4 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc3s200-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s200-tq144-4 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc3s200-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd

Software Quality
Run Statistics
Program Name	Runs Started	Runs Finished	Errors	Fatal Errors	Internal Errors	Exceptions	Core Dumps
Start	0	0	0	0	0	0	0
_impact	98	76	0	0	0	0	0
arwz	5	5	0	0	0	0	0
bitgen	772	767	0	0	0	0	0
edif2ngd	1	1	0	0	0	0	0
map	923	788	0	0	0	0	0
netgen	9	9	0	0	0	0	0
ngc2edif	3	3	0	0	0	0	0
ngcbuild	9	9	0	0	0	0	0
ngdbuild	995	984	0	0	0	0	0
obngc	9	9	0	0	0	0	0
par	785	780	3	0	0	0	0
trce	757	757	0	0	0	0	0
xst	1476	1367	0	0	0	0	0

Help Statistics
Help files
/doc/usenglish/isehelp/pn_db_nsw_select_ip.htm ( 1 )

Project Statistics
PROP_Enable_Message_Filtering=false	PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced	PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false	PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog)	PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL	PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Constraints Editor	PROP_intProjectCreationTimestamp=2015-02-09T14:13:10
PROP_intWbtProjectID=A26913821B0D4A4E8EA1AD2F2A4DCB4D	PROP_intWbtProjectIteration=6
PROP_intWorkingDirLocWRTProjDir=Same	PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed	PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=true	PROP_DevFamily=Spartan3
PROP_DevDevice=xc3s200	PROP_DevFamilyPMName=spartan3
PROP_DevPackage=tq144	PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4	PROP_PreferredLanguage=Verilog
FILE_UCF=1	FILE_VERILOG=1

Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1	NGDBUILD_NUM_FDE=59	NGDBUILD_NUM_FDRE=63	NGDBUILD_NUM_FDRSE=1
NGDBUILD_NUM_GND=1	NGDBUILD_NUM_IBUF=1	NGDBUILD_NUM_INV=5	NGDBUILD_NUM_LUT1=28
NGDBUILD_NUM_LUT2=13	NGDBUILD_NUM_LUT2_L=1	NGDBUILD_NUM_LUT3=47	NGDBUILD_NUM_LUT3_D=6
NGDBUILD_NUM_LUT3_L=2	NGDBUILD_NUM_LUT4=58	NGDBUILD_NUM_LUT4_D=4	NGDBUILD_NUM_LUT4_L=1
NGDBUILD_NUM_MUXCY=50	NGDBUILD_NUM_MUXF5=9	NGDBUILD_NUM_OBUF=1	NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=47
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1	NGDBUILD_NUM_FDE=59	NGDBUILD_NUM_FDRE=63	NGDBUILD_NUM_FDRSE=1
NGDBUILD_NUM_GND=1	NGDBUILD_NUM_IBUF=1	NGDBUILD_NUM_IBUFG=1	NGDBUILD_NUM_INV=5
NGDBUILD_NUM_LUT1=28	NGDBUILD_NUM_LUT2=13	NGDBUILD_NUM_LUT2_L=1	NGDBUILD_NUM_LUT3=47
NGDBUILD_NUM_LUT3_D=6	NGDBUILD_NUM_LUT3_L=2	NGDBUILD_NUM_LUT4=58	NGDBUILD_NUM_LUT4_D=4
NGDBUILD_NUM_LUT4_L=1	NGDBUILD_NUM_MUXCY=50	NGDBUILD_NUM_MUXF5=9	NGDBUILD_NUM_OBUF=1
NGDBUILD_NUM_TS_TIMESPEC=1	NGDBUILD_NUM_VCC=1	NGDBUILD_NUM_XORCY=47

XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj	-ifmt=mixed	-ofn=<design_top>	-ofmt=NGC
-p=xc3s200-4-tq144	-top=<design_top>	-opt_mode=Speed	-opt_level=1
-iuc=NO	-keep_hierarchy=No	-netlist_hierarchy=As_Optimized	-rtlview=Yes
-glob_opt=AllClockNets	-read_cores=YES	-write_timing_constraints=NO	-cross_clock_analysis=NO
-bus_delimiter=<>	-slice_utilization_ratio=100	-bram_utilization_ratio=100	-verilog2001=YES
-fsm_extract=YES	-fsm_encoding=Auto	-safe_implementation=No	-fsm_style=LUT
-ram_extract=Yes	-ram_style=Auto	-rom_extract=Yes	-shreg_extract=YES
-rom_style=Auto	-auto_bram_packing=NO	-resource_sharing=YES	-async_to_sync=NO
-mult_style=Auto	-iobuf=YES	-max_fanout=500	-bufg=8
-register_duplication=YES	-register_balancing=No	-optimize_primitives=NO	-use_clock_enable=Yes
-use_sync_set=Yes	-use_sync_reset=Yes	-iob=Auto	-equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5