Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.2 (WebPack) - P.28xd Target Family: Spartan3
OS Platform: NT64 Target Device: xc3s200
Project ID (random number) ea081235f4e2469da4cf3e33d5a71d61.AE9513ECEF13431AAD9CC320D1C53F48.2 Target Package: tq144
Registration ID __0_0_0 Target Speed: -4
Date Generated 2015-04-18T14:30:07 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i5-4670 CPU @ 3.40GHz CPU Speed 3392 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=3
  • 16-bit adder=1
  • 4-bit adder=1
  • 8-bit adder=1
 Comparators=4
  • 32-bit comparator equal=1
  • 32-bit comparator not equal=1
  • 5-bit comparator greater=1
  • 5-bit comparator lessequal=1
 Counters=3
  • 2-bit up counter=1
  • 32-bit up counter=1
  • 8-bit up counter=1
 ROMs=2
  • 25x8-bit ROM=1
  • 81x8-bit ROM=1
 Registers=63
  • Flip-Flops=63
 		MiscellaneousStatistics
  • AGG_BONDED_IO=3
  • AGG_IO=3
  • AGG_SLICE=98
  • NUM_4_INPUT_LUT=183
  • NUM_BONDED_IOB=3
  • NUM_BUFGMUX=1
  • NUM_CYMUX=65
  • NUM_LUT_RT=48
  • NUM_SLICEL=98
  • NUM_SLICE_FF=75
  • NUM_XOR=56
 		NetStatistics
  • NumNets_Active=200
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=43
  • NumNodesOfType_Active_CNTRLPIN=74
  • NumNodesOfType_Active_DOUBLE=321
  • NumNodesOfType_Active_DUMMY=518
  • NumNodesOfType_Active_DUMMYESC=1
  • NumNodesOfType_Active_GLOBAL=13
  • NumNodesOfType_Active_HUNIHEX=3
  • NumNodesOfType_Active_INPUT=563
  • NumNodesOfType_Active_IOBOUTPUT=1
  • NumNodesOfType_Active_OMUX=184
  • NumNodesOfType_Active_OUTPUT=196
  • NumNodesOfType_Active_PREBXBY=14
  • NumNodesOfType_Active_VFULLHEX=1
  • NumNodesOfType_Active_VUNIHEX=8
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_INPUT=3
  • NumNodesOfType_Vcc_PREBXBY=3
  • NumNodesOfType_Vcc_VCCOUT=4
 SiteStatistics
  • IOB-DIFFM=2
  • IOB-DIFFS=1
  • SLICEL-SLICEM=41
 		SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IOB=3
  • IOB_INBUF=2
  • IOB_OUTBUF=1
  • IOB_PAD=3
  • SLICEL=98
  • SLICEL_C1VDD=3
  • SLICEL_CYMUXF=34
  • SLICEL_CYMUXG=31
  • SLICEL_F=94
  • SLICEL_F5MUX=12
  • SLICEL_FFX=37
  • SLICEL_FFY=38
  • SLICEL_G=89
  • SLICEL_GNDF=31
  • SLICEL_GNDG=31
  • SLICEL_XORF=28
  • SLICEL_XORG=28
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
 BUFIO2FB_BUFIO2FB
  • DIVIDE_BYPASS=[TRUE:1]
  • INVERT_INPUTS=[FALSE:1]
 BUFIO2_BUFIO2
  • DIVIDE=[1:1]
  • DIVIDE_BYPASS=[TRUE:1]
  • I_INVERT=[FALSE:1]
 DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • RST=[RST:1] [RST_INV:0]
 DCM_DCM
  • CLKDV_DIVIDE=[2.0:1]
  • CLKIN_DIVIDE_BY_2=[FALSE:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[5:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DSS_MODE=[NONE:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • RST=[RST:1] [RST_INV:0]
  • STARTUP_WAIT=[FALSE:1]
  • VERY_HIGH_FREQUENCY=[FALSE:1]
 FF_SR
  • CK=[CK:3] [CK_INV:0]
  • SRINIT=[SRINIT0:3]
  • SYNC_ATTR=[SYNC:3]
 IOB
  • O1=[O1_INV:0] [O1:1]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:1]
 IOB_PAD
  • DRIVEATTRBOX=[12:1]
  • IOATTRBOX=[LVCMOS33:3]
  • SLEW=[SLOW:1]
 RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • ENAWREN=[ENAWREN:0] [ENAWREN_INV:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
 RAMB8BWER_RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • DATA_WIDTH_A=[9:1]
  • DATA_WIDTH_B=[0:1]
  • DOA_REG=[0:1]
  • DOB_REG=[0:1]
  • ENAWREN=[ENAWREN:0] [ENAWREN_INV:1]
  • EN_RSTRAM_A=[TRUE:1]
  • EN_RSTRAM_B=[TRUE:1]
  • RAM_MODE=[TDP:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTTYPE=[SYNC:1]
  • RST_PRIORITY_A=[CE:1]
  • RST_PRIORITY_B=[CE:1]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
  • WRITE_MODE_A=[WRITE_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1]
 REG_SR
  • CK=[CK:68] [CK_INV:0]
  • LATCH_OR_FF=[FF:68]
  • SRINIT=[SRINIT0:67] [SRINIT1:1]
  • SYNC_ATTR=[ASYNC:54] [SYNC:14]
 SLICEL
  • BX=[BX_INV:0] [BX:16]
  • BY=[BY:4] [BY_INV:1]
  • CE=[CE:40] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:30]
  • CLK=[CLK:43] [CLK_INV:0]
  • SR=[SR:34] [SR_INV:0]
 SLICEL_CYMUXF
  • 0=[0:34] [0_INV:0]
  • 1=[1_INV:0] [1:34]
 SLICEL_CYMUXG
  • 0=[0:31] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:12] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:36] [CE_INV:0]
  • CK=[CK:37] [CK_INV:0]
  • D=[D:37] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:37]
  • FFX_SR_ATTR=[SRLOW:37]
  • LATCH_OR_FF=[FF:37]
  • SR=[SR:32] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:5] [SYNC:32]
 SLICEL_FFY
  • CE=[CE:36] [CE_INV:0]
  • CK=[CK:38] [CK_INV:0]
  • D=[D:37] [D_INV:1]
  • FFY_INIT_ATTR=[INIT0:37] [INIT1:1]
  • FFY_SR_ATTR=[SRLOW:38]
  • LATCH_OR_FF=[FF:38]
  • REV=[REV_INV:0] [REV:1]
  • SR=[SR:32] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:6] [SYNC:32]
 SLICEL_XORF
  • 1=[1_INV:0] [1:28]
 SLICEX
  • CLK=[CLK:24] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=2
  • O=2
 BUFGMUX
  • I0=1
  • O=1
  • S=1
 BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
 BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
 BUFG_BUFG
  • I0=2
  • O=2
 BUFIO2
  • DIVCLK=1
  • I=1
 BUFIO2FB
  • I=1
  • O=1
 BUFIO2FB_BUFIO2FB
  • I=1
  • O=1
 BUFIO2_BUFIO2
  • DIVCLK=1
  • I=1
 CARRY4
  • CIN=12
  • CO3=12
  • CYINIT=2
  • DI0=12
  • DI1=13
  • DI2=12
  • DI3=12
  • O0=11
  • O1=11
  • O2=11
  • O3=10
  • S0=14
  • S1=13
  • S2=13
  • S3=12
 DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
 DCM_DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
 FF_SR
  • CE=2
  • CK=3
  • D=3
  • Q=3
  • SR=3
 HARD0
  • 0=2
 IOB
  • I=2
  • O1=1
  • PAD=3
 IOB_IMUX
  • I=2
  • OUT=2
 IOB_INBUF
  • IN=2
  • OUT=2
 IOB_OUTBUF
  • IN=1
  • OUT=1
 IOB_PAD
  • PAD=3
 LUT5
  • A1=6
  • A2=6
  • A3=11
  • A4=9
  • A5=10
  • O5=57
 LUT6
  • A1=76
  • A2=94
  • A3=101
  • A4=112
  • A5=151
  • A6=155
  • O6=157
 PAD
  • PAD=3
 RAMB8BWER
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR3=1
  • ADDRAWRADDR4=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • CLKAWRCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIPADIP0=1
  • DOADO0=1
  • DOADO1=1
  • DOADO2=1
  • DOADO3=1
  • DOADO4=1
  • DOADO5=1
  • DOADO6=1
  • DOADO7=1
  • ENAWREN=1
  • REGCEA=1
  • RSTA=1
  • WEAWEL0=1
  • WEAWEL1=1
 RAMB8BWER_RAMB8BWER
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR3=1
  • ADDRAWRADDR4=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • CLKAWRCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIPADIP0=1
  • DOADO0=1
  • DOADO1=1
  • DOADO2=1
  • DOADO3=1
  • DOADO4=1
  • DOADO5=1
  • DOADO6=1
  • DOADO7=1
  • ENAWREN=1
  • REGCEA=1
  • RSTA=1
  • WEAWEL0=1
  • WEAWEL1=1
 REG_SR
  • CE=19
  • CK=68
  • D=68
  • Q=68
  • SR=14
 SELMUX2_1
  • 0=1
  • 1=1
  • OUT=1
  • S0=1
 SLICEL
  • BX=16
  • BY=5
  • CE=40
  • CIN=30
  • CLK=43
  • COUT=31
  • F1=94
  • F2=70
  • F3=62
  • F4=47
  • G1=89
  • G2=62
  • G3=54
  • G4=39
  • SR=34
  • X=51
  • XQ=37
  • Y=37
  • YQ=38
 SLICEL_C1VDD
  • 1=3
 SLICEL_CYMUXF
  • 0=34
  • 1=34
  • OUT=34
  • S0=34
 SLICEL_CYMUXG
  • 0=31
  • 1=31
  • OUT=31
  • S0=31
 SLICEL_F
  • A1=94
  • A2=70
  • A3=62
  • A4=47
  • D=94
 SLICEL_F5MUX
  • F=12
  • G=12
  • OUT=12
  • S0=12
 SLICEL_FFX
  • CE=36
  • CK=37
  • D=37
  • Q=37
  • SR=32
 SLICEL_FFY
  • CE=36
  • CK=38
  • D=38
  • Q=38
  • REV=1
  • SR=32
 SLICEL_G
  • A1=89
  • A2=62
  • A3=54
  • A4=39
  • D=89
 SLICEL_GNDF
  • 0=31
 SLICEL_GNDG
  • 0=31
 SLICEL_XORF
  • 0=28
  • 1=28
  • O=28
 SLICEL_XORG
  • 0=28
  • 1=28
  • O=28
 SLICEX
  • A=7
  • A1=19
  • A2=25
  • A3=26
  • A4=28
  • A5=27
  • A6=27
  • AMUX=3
  • AQ=21
  • B=10
  • B1=20
  • B2=25
  • B3=25
  • B4=26
  • B5=25
  • B6=26
  • BMUX=2
  • BQ=16
  • C=9
  • C1=16
  • C2=19
  • C3=23
  • C4=25
  • C5=25
  • C6=25
  • CE=7
  • CLK=24
  • CMUX=3
  • CQ=17
  • CX=1
  • D=9
  • D1=12
  • D2=15
  • D3=18
  • D4=21
  • D5=21
  • D6=22
  • DMUX=3
  • DQ=13
  • SR=6
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s200-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s200-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
Start 0 0 0 0 0 0 0
_impact 98 76 0 0 0 0 0
arwz 5 5 0 0 0 0 0
bitgen 776 771 0 0 0 0 0
edif2ngd 1 1 0 0 0 0 0
map 930 793 0 0 0 0 0
netgen 9 9 0 0 0 0 0
ngc2edif 3 3 0 0 0 0 0
ngcbuild 9 9 0 0 0 0 0
ngdbuild 1010 999 0 0 0 0 0
obngc 9 9 0 0 0 0 0
par 789 784 3 0 0 0 0
trce 761 761 0 0 0 0 0
xst 1484 1375 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/pn_db_nsw_select_ip.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Constraints Editor PROP_intProjectCreationTimestamp=2015-02-12T22:07:29
PROP_intWbtProjectID=AE9513ECEF13431AAD9CC320D1C53F48 PROP_intWbtProjectIteration=2
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan3 PROP_DevDevice=xc3s200
PROP_DevFamilyPMName=spartan3 PROP_DevPackage=tq144
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=Verilog FILE_UCF=1
FILE_VERILOG=2
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDE=11 NGDBUILD_NUM_FDR=2 NGDBUILD_NUM_FDRE=61
NGDBUILD_NUM_FDRS=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_INV=4 NGDBUILD_NUM_LUT1=48
NGDBUILD_NUM_LUT2=12 NGDBUILD_NUM_LUT2_D=1 NGDBUILD_NUM_LUT2_L=3 NGDBUILD_NUM_LUT3=26
NGDBUILD_NUM_LUT3_L=4 NGDBUILD_NUM_LUT4=76 NGDBUILD_NUM_LUT4_D=1 NGDBUILD_NUM_LUT4_L=9
NGDBUILD_NUM_MUXCY=65 NGDBUILD_NUM_MUXF5=12 NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=56
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDE=11 NGDBUILD_NUM_FDR=2 NGDBUILD_NUM_FDRE=61
NGDBUILD_NUM_FDRS=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=4 NGDBUILD_NUM_LUT1=48 NGDBUILD_NUM_LUT2=12 NGDBUILD_NUM_LUT2_D=1
NGDBUILD_NUM_LUT2_L=3 NGDBUILD_NUM_LUT3=26 NGDBUILD_NUM_LUT3_L=4 NGDBUILD_NUM_LUT4=76
NGDBUILD_NUM_LUT4_D=1 NGDBUILD_NUM_LUT4_L=9 NGDBUILD_NUM_MUXCY=65 NGDBUILD_NUM_MUXF5=12
NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=56
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s200-4-tq144 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=8
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5