| Project Statistics |
| PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
| PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
| PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
| PROP_SelectedInstanceHierarchicalPath=/testbench |
PROP_Simulator=ISim (VHDL/Verilog) |
| PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
| PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Constraints Editor |
| PROP_intProjectCreationTimestamp=2015-02-04T11:14:56 |
PROP_intWbtProjectID=3722FAFE96224B4EBBD6E0B7A5AA6440 |
| PROP_intWbtProjectIteration=53 |
PROP_intWorkingDirLocWRTProjDir=Same |
| PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
| PROP_selectedSimRootSourceNode_behav=work.testbench |
PROP_xilxBitgCfg_Rate_spartan6=6 |
| PROP_xilxBitgStart_IntDone=true |
PROP_AutoTop=false |
| PROP_DevFamily=Spartan3 |
PROP_DevDevice=xc3s200 |
| PROP_DevFamilyPMName=spartan3 |
PROP_DevPackage=tq144 |
| PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
| PROP_PreferredLanguage=Verilog |
FILE_UCF=1 |
| FILE_VERILOG=3 |