Device Usage Statistics Report

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.

Software Version and Target Device
Product Version:	ISE:14.2 (WebPack) - P.28xd	Target Family:	Spartan3
OS Platform:	NT64	Target Device:	xc3s200
Project ID (random number)	ea081235f4e2469da4cf3e33d5a71d61.08525F0BC2C34B09908E4E56486E49DE.6	Target Package:	tq144
Registration ID	__0_0_0	Target Speed:	-4
Date Generated	2015-04-18T14:37:26	Tool Flow	ISE

User Environment
OS Name	Microsoft Windows 7 , 64-bit	OS Release	Service Pack 1 (build 7601)
CPU Name	Intel(R) Core(TM) i5-4670 CPU @ 3.40GHz	CPU Speed	3392 MHz

Device Usage Statistics
Macro Statistics	Miscellaneous Statistics	Net Statistics	Site Usage
Adders/Subtractors=163 32-bit adder=1 4-bit adder=144 6-bit adder carry out=18 Comparators=154 4-bit comparator greater=144 5-bit comparator lessequal=9 8-bit comparator less=1 Counters=4 2-bit up counter=1 32-bit up counter=1 32-bit updown counter=1 9-bit up counter=1 Multiplexers=2 1-bit 4-to-1 multiplexer=2 Registers=13 Flip-Flops=13	MiscellaneousStatistics AGG_BONDED_IO=13 AGG_IO=13 AGG_SLICE=494 NUM_4_INPUT_LUT=904 NUM_BONDED_IOB=13 NUM_BUFGMUX=1 NUM_CYMUX=109 NUM_LUT_RT=40 NUM_SLICEL=494 NUM_SLICE_FF=88 NUM_XOR=105	NetStatistics NumNets_Active=969 NumNets_Gnd=1 NumNets_Vcc=1 NumNodesOfType_Active_CLKPIN=47 NumNodesOfType_Active_CNTRLPIN=65 NumNodesOfType_Active_DOUBLE=1518 NumNodesOfType_Active_DUMMY=3186 NumNodesOfType_Active_DUMMYESC=3 NumNodesOfType_Active_GLOBAL=20 NumNodesOfType_Active_HFULLHEX=6 NumNodesOfType_Active_HUNIHEX=33 NumNodesOfType_Active_INPUT=3272 NumNodesOfType_Active_IOBOUTPUT=3 NumNodesOfType_Active_OMUX=938 NumNodesOfType_Active_OUTPUT=954 NumNodesOfType_Active_PREBXBY=24 NumNodesOfType_Active_VFULLHEX=20 NumNodesOfType_Active_VUNIHEX=49 NumNodesOfType_Gnd_DOUBLE=2 NumNodesOfType_Gnd_INPUT=4 NumNodesOfType_Gnd_OMUX=3 NumNodesOfType_Gnd_OUTPUT=4 NumNodesOfType_Gnd_PREBXBY=4 SiteStatistics IOB-DIFFM=6 IOB-DIFFS=7 SLICEL-SLICEM=259	SiteSummary BUFGMUX=1 BUFGMUX_GCLKMUX=1 BUFGMUX_GCLK_BUFFER=1 IOB=13 IOB_INBUF=3 IOB_OUTBUF=10 IOB_PAD=13 SLICEL=494 SLICEL_C1VDD=3 SLICEL_CYMUXF=56 SLICEL_CYMUXG=53 SLICEL_F=486 SLICEL_F5MUX=12 SLICEL_FFX=43 SLICEL_FFY=45 SLICEL_G=418 SLICEL_GNDF=37 SLICEL_GNDG=38 SLICEL_XORF=53 SLICEL_XORG=52

Configuration Data
BUFGMUX S=[S_INV:1] [S:0] BUFGMUX_GCLKMUX DISABLE_ATTR=[LOW:1] S=[S_INV:1] [S:0] BUFIO2FB_BUFIO2FB DIVIDE_BYPASS=[TRUE:1] INVERT_INPUTS=[FALSE:1] BUFIO2_BUFIO2 DIVIDE=[1:1] DIVIDE_BYPASS=[TRUE:1] I_INVERT=[FALSE:1] DCM PSCLK=[PSCLK_INV:0] [PSCLK:1] PSEN=[PSEN_INV:0] [PSEN:1] PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0] RST=[RST:1] [RST_INV:0] DCM_DCM CLKDV_DIVIDE=[2.0:1] CLKIN_DIVIDE_BY_2=[FALSE:1] CLKOUT_PHASE_SHIFT=[NONE:1] CLK_FEEDBACK=[1X:1] DESKEW_ADJUST=[5:1] DFS_FREQUENCY_MODE=[LOW:1] DLL_FREQUENCY_MODE=[LOW:1] DSS_MODE=[NONE:1] DUTY_CYCLE_CORRECTION=[TRUE:1] PSCLK=[PSCLK_INV:0] [PSCLK:1] PSEN=[PSEN_INV:0] [PSEN:1] PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0] RST=[RST:1] [RST_INV:0] STARTUP_WAIT=[FALSE:1] VERY_HIGH_FREQUENCY=[FALSE:1]	FF_SR CK=[CK:5] [CK_INV:0] SRINIT=[SRINIT0:5] SYNC_ATTR=[ASYNC:5] IOB O1=[O1_INV:1] [O1:9] IOB_OUTBUF IN=[IN_INV:1] [IN:9] IOB_PAD DRIVEATTRBOX=[12:10] IOATTRBOX=[LVCMOS33:13] SLEW=[SLOW:10] REG_SR CK=[CK:66] [CK_INV:0] LATCH_OR_FF=[FF:66] SRINIT=[SRINIT0:65] [SRINIT1:1] SYNC_ATTR=[ASYNC:32] [SYNC:34] SLICEL BX=[BX_INV:0] [BX:21] BY=[BY:7] [BY_INV:1] CE=[CE:24] [CE_INV:1] CIN=[CIN_INV:0] [CIN:52] CLK=[CLK:47] [CLK_INV:0] SR=[SR:40] [SR_INV:0]	SLICEL_CYMUXF 0=[0:56] [0_INV:0] 1=[1_INV:0] [1:56] SLICEL_CYMUXG 0=[0:53] [0_INV:0] SLICEL_F5MUX S0=[S0:12] [S0_INV:0] SLICEL_FFX CE=[CE:22] [CE_INV:1] CK=[CK:43] [CK_INV:0] D=[D:43] [D_INV:0] FFX_INIT_ATTR=[INIT0:43] FFX_SR_ATTR=[SRLOW:43] LATCH_OR_FF=[FF:43] SR=[SR:39] [SR_INV:0] SYNC_ATTR=[ASYNC:9] [SYNC:34] SLICEL_FFY CE=[CE:24] [CE_INV:1] CK=[CK:45] [CK_INV:0] D=[D:44] [D_INV:1] FFY_INIT_ATTR=[INIT0:44] [INIT1:1] FFY_SR_ATTR=[SRLOW:45] LATCH_OR_FF=[FF:45] SR=[SR:38] [SR_INV:0] SYNC_ATTR=[ASYNC:13] [SYNC:32]	SLICEL_XORF 1=[1_INV:0] [1:53] SLICEX CLK=[CLK:18] [CLK_INV:0]

Pin Data
BUFG I0=2 O=2 BUFGMUX I0=1 O=1 S=1 BUFGMUX_GCLKMUX I0=1 OUT=1 S=1 BUFGMUX_GCLK_BUFFER IN=1 OUT=1 BUFG_BUFG I0=2 O=2 BUFIO2 DIVCLK=1 I=1 BUFIO2FB I=1 O=1 BUFIO2FB_BUFIO2FB I=1 O=1 BUFIO2_BUFIO2 DIVCLK=1 I=1 CARRY4 CIN=19 CO3=19 CYINIT=4 DI0=22 DI1=22 DI2=22 DI3=19 O0=23 O1=22 O2=22 O3=22 S0=23 S1=22 S2=22 S3=22 DCM CLK0=1 CLKFB=1 CLKFX=1 CLKIN=1 PSCLK=1 PSEN=1 PSINCDEC=1 RST=1 DCM_DCM CLK0=1 CLKFB=1 CLKFX=1 CLKIN=1 PSCLK=1 PSEN=1 PSINCDEC=1 RST=1	FF_SR CK=5 D=5 Q=5 HARD0 0=2 IOB I=3 O1=10 PAD=13 IOB_IMUX I=3 OUT=3 IOB_INBUF IN=3 OUT=3 IOB_OUTBUF IN=10 OUT=10 IOB_PAD PAD=13 LUT5 A1=44 A2=46 A3=37 A4=29 A5=28 O5=104 LUT6 A1=463 A2=519 A3=549 A4=557 A5=609 A6=615 O6=618 PAD PAD=13 REG_SR CE=48 CK=66 D=66 Q=66 SR=45 SELMUX2_1 0=3 1=3 OUT=3 S0=3 SLICEL BX=21 BY=8 CE=25 CIN=52 CLK=47 COUT=53 F1=486 F2=449 F3=421 F4=380 G1=416 G2=381 G3=357 G4=295 SR=40 X=443 XQ=43 Y=368 YQ=45	SLICEL_C1VDD 1=3 SLICEL_CYMUXF 0=56 1=56 OUT=56 S0=56 SLICEL_CYMUXG 0=53 1=53 OUT=53 S0=53 SLICEL_F A1=486 A2=449 A3=421 A4=380 D=486 SLICEL_F5MUX F=12 G=12 OUT=12 S0=12 SLICEL_FFX CE=23 CK=43 D=43 Q=43 SR=39 SLICEL_FFY CE=25 CK=45 D=45 Q=45 SR=38 SLICEL_G A1=416 A2=381 A3=357 A4=295 D=418 SLICEL_GNDF 0=37 SLICEL_GNDG 0=38 SLICEL_XORF 0=53 1=53 O=53 SLICEL_XORG 0=52 1=52 O=52 SLICEX A=135 A1=124 A2=131 A3=132 A4=135 A5=137 A6=138 AMUX=11 AQ=10 AX=5 B=95 B1=88 B2=92 B3=95 B4=96 B5=98 B6=99 BMUX=6 BQ=6 BX=2 C=129 C1=125 C2=127 C3=129 C4=129 C5=132 C6=132 CE=6 CLK=18 CMUX=12 CQ=5 CX=2 D=144 D1=136 D2=143 D3=143 D4=144 D5=146 D6=147 DMUX=20 DQ=4 DX=1 SR=4

Tool Usage

Command Line History

xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s200-tq144-4 <fname>.ngc <fname>.ngd
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s200-tq144-4 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc3s200-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd

Software Quality
Run Statistics
Program Name	Runs Started	Runs Finished	Errors	Fatal Errors	Internal Errors	Exceptions	Core Dumps
Start	0	0	0	0	0	0	0
_impact	98	76	0	0	0	0	0
arwz	5	5	0	0	0	0	0
bitgen	778	773	0	0	0	0	0
edif2ngd	1	1	0	0	0	0	0
map	932	795	0	0	0	0	0
netgen	9	9	0	0	0	0	0
ngc2edif	3	3	0	0	0	0	0
ngcbuild	9	9	0	0	0	0	0
ngdbuild	1014	1003	0	0	0	0	0
obngc	9	9	0	0	0	0	0
par	791	786	3	0	0	0	0
trce	763	763	0	0	0	0	0
xst	1489	1380	0	0	0	0	0

Help Statistics
Help files
/doc/usenglish/isehelp/pn_db_nsw_select_ip.htm ( 1 )

Project Statistics
PROP_Enable_Message_Filtering=false	PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced	PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false	PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog)	PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL	PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Constraints Editor	PROP_intProjectCreationTimestamp=2015-02-13T19:53:45
PROP_intWbtProjectID=08525F0BC2C34B09908E4E56486E49DE	PROP_intWbtProjectIteration=6
PROP_intWorkingDirLocWRTProjDir=Same	PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone=true	PROP_AutoTop=true
PROP_DevFamily=Spartan3	PROP_DevDevice=xc3s200
PROP_DevFamilyPMName=spartan3	PROP_DevPackage=tq144
PROP_Synthesis_Tool=XST (VHDL/Verilog)	PROP_DevSpeed=-4
PROP_PreferredLanguage=Verilog	FILE_UCF=1
FILE_VERILOG=4

Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1	NGDBUILD_NUM_FD=6	NGDBUILD_NUM_FDCE=11	NGDBUILD_NUM_FDE=5
NGDBUILD_NUM_FDR=34	NGDBUILD_NUM_FDRE=32	NGDBUILD_NUM_GND=1	NGDBUILD_NUM_IBUF=2
NGDBUILD_NUM_INV=35	NGDBUILD_NUM_LUT1=40	NGDBUILD_NUM_LUT2=52	NGDBUILD_NUM_LUT3=102
NGDBUILD_NUM_LUT3_D=1	NGDBUILD_NUM_LUT4=674	NGDBUILD_NUM_LUT4_D=1	NGDBUILD_NUM_MUXCY=109
NGDBUILD_NUM_MUXF5=12	NGDBUILD_NUM_OBUF=10	NGDBUILD_NUM_VCC=1	NGDBUILD_NUM_XORCY=105
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1	NGDBUILD_NUM_FD=6	NGDBUILD_NUM_FDCE=11	NGDBUILD_NUM_FDE=5
NGDBUILD_NUM_FDR=34	NGDBUILD_NUM_FDRE=32	NGDBUILD_NUM_GND=1	NGDBUILD_NUM_IBUF=2
NGDBUILD_NUM_IBUFG=1	NGDBUILD_NUM_INV=35	NGDBUILD_NUM_LUT1=40	NGDBUILD_NUM_LUT2=52
NGDBUILD_NUM_LUT3=102	NGDBUILD_NUM_LUT3_D=1	NGDBUILD_NUM_LUT4=674	NGDBUILD_NUM_LUT4_D=1
NGDBUILD_NUM_MUXCY=109	NGDBUILD_NUM_MUXF5=12	NGDBUILD_NUM_OBUF=10	NGDBUILD_NUM_TS_TIMESPEC=1
NGDBUILD_NUM_VCC=1	NGDBUILD_NUM_XORCY=105

XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj	-ifmt=mixed	-ofn=<design_top>	-ofmt=NGC
-p=xc3s200-4-tq144	-top=<design_top>	-opt_mode=Speed	-opt_level=1
-iuc=NO	-keep_hierarchy=No	-netlist_hierarchy=As_Optimized	-rtlview=Yes
-glob_opt=AllClockNets	-read_cores=YES	-write_timing_constraints=NO	-cross_clock_analysis=NO
-bus_delimiter=<>	-slice_utilization_ratio=100	-bram_utilization_ratio=100	-verilog2001=YES
-fsm_extract=YES	-fsm_encoding=Auto	-safe_implementation=No	-fsm_style=LUT
-ram_extract=Yes	-ram_style=Auto	-rom_extract=Yes	-shreg_extract=YES
-rom_style=Auto	-auto_bram_packing=NO	-resource_sharing=YES	-async_to_sync=NO
-mult_style=Auto	-iobuf=YES	-max_fanout=500	-bufg=8
-register_duplication=YES	-register_balancing=No	-optimize_primitives=NO	-use_clock_enable=Yes
-use_sync_set=Yes	-use_sync_reset=Yes	-iob=Auto	-equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5