Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.2 (WebPack) - P.28xd Target Family: Spartan3
OS Platform: NT64 Target Device: xc3s200
Project ID (random number) ea081235f4e2469da4cf3e33d5a71d61.D4D675BE606849FC80D8810D46929BC7.3 Target Package: tq144
Registration ID __0_0_0 Target Speed: -4
Date Generated 2015-04-18T14:33:59 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i5-4670 CPU @ 3.40GHz CPU Speed 3392 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=1
  • 28-bit comparator greater=1
 Counters=2
  • 2-bit up counter=1
  • 28-bit up counter=1
 Registers=3
  • Flip-Flops=3
 		MiscellaneousStatistics
  • AGG_BONDED_IO=3
  • AGG_IO=3
  • AGG_SLICE=31
  • NUM_4_INPUT_LUT=53
  • NUM_BONDED_IOB=3
  • NUM_BUFGMUX=1
  • NUM_CYMUX=47
  • NUM_LUT_RT=31
  • NUM_SLICEL=31
  • NUM_SLICE_FF=33
  • NUM_XOR=28
 		NetStatistics
  • NumNets_Active=66
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=18
  • NumNodesOfType_Active_CNTRLPIN=34
  • NumNodesOfType_Active_DOUBLE=94
  • NumNodesOfType_Active_DUMMY=95
  • NumNodesOfType_Active_DUMMYESC=1
  • NumNodesOfType_Active_GLOBAL=7
  • NumNodesOfType_Active_HFULLHEX=1
  • NumNodesOfType_Active_HUNIHEX=1
  • NumNodesOfType_Active_INPUT=122
  • NumNodesOfType_Active_IOBOUTPUT=1
  • NumNodesOfType_Active_OMUX=65
  • NumNodesOfType_Active_OUTPUT=62
  • NumNodesOfType_Active_PREBXBY=3
  • NumNodesOfType_Active_VFULLHEX=4
  • NumNodesOfType_Active_VUNIHEX=2
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_INPUT=2
  • NumNodesOfType_Vcc_PREBXBY=2
  • NumNodesOfType_Vcc_VCCOUT=3
 SiteStatistics
  • IOB-DIFFM=2
  • IOB-DIFFS=1
  • SLICEL-SLICEM=23
 		SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IOB=3
  • IOB_INBUF=1
  • IOB_OUTBUF=2
  • IOB_PAD=3
  • SLICEL=31
  • SLICEL_C1VDD=3
  • SLICEL_C2VDD=4
  • SLICEL_CYMUXF=25
  • SLICEL_CYMUXG=22
  • SLICEL_F=27
  • SLICEL_FFX=15
  • SLICEL_FFY=18
  • SLICEL_G=26
  • SLICEL_GNDF=22
  • SLICEL_GNDG=18
  • SLICEL_XORF=14
  • SLICEL_XORG=14
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
 FF_SR
  • CK=[CK:1] [CK_INV:0]
  • SRINIT=[SRINIT1:1]
  • SYNC_ATTR=[ASYNC:1]
 IOB
  • O1=[O1_INV:0] [O1:2]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:2]
 IOB_PAD
  • DRIVEATTRBOX=[12:2]
  • IOATTRBOX=[LVCMOS33:3]
  • SLEW=[SLOW:2]
 REG_SR
  • CK=[CK:32] [CK_INV:0]
  • LATCH_OR_FF=[FF:32]
  • SRINIT=[SRINIT0:31] [SRINIT1:1]
  • SYNC_ATTR=[ASYNC:32]
 SLICEL
  • BX=[BX_INV:0] [BX:3]
  • BY=[BY:1] [BY_INV:3]
  • CE=[CE:4] [CE_INV:14]
  • CIN=[CIN_INV:0] [CIN:22]
  • CLK=[CLK:18] [CLK_INV:0]
  • SR=[SR:16] [SR_INV:0]
 SLICEL_CYMUXF
  • 0=[0:25] [0_INV:0]
  • 1=[1_INV:0] [1:25]
 SLICEL_CYMUXG
  • 0=[0:22] [0_INV:0]
 SLICEL_FFX
  • CE=[CE:1] [CE_INV:14]
  • CK=[CK:15] [CK_INV:0]
  • D=[D:15] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:15]
  • FFX_SR_ATTR=[SRLOW:15]
  • LATCH_OR_FF=[FF:15]
  • SR=[SR:14] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:1] [SYNC:14]
 SLICEL_FFY
  • CE=[CE:4] [CE_INV:14]
  • CK=[CK:18] [CK_INV:0]
  • D=[D:15] [D_INV:3]
  • FFY_INIT_ATTR=[INIT0:16] [INIT1:2]
  • FFY_SR_ATTR=[SRLOW:17] [SRHIGH:1]
  • LATCH_OR_FF=[FF:18]
  • SR=[SR:16] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:2] [SYNC:16]
 SLICEL_XORF
  • 1=[1_INV:0] [1:14]
 SLICEX
  • CLK=[CLK:10] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
 BUFGMUX
  • I0=1
  • O=1
  • S=1
 BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
 BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
 BUFG_BUFG
  • I0=1
  • O=1
 CARRY4
  • CIN=7
  • CO0=1
  • CO3=7
  • CYINIT=2
  • DI0=9
  • DI1=8
  • DI2=8
  • DI3=7
  • O0=7
  • O1=7
  • O2=7
  • O3=7
  • S0=9
  • S1=8
  • S2=8
  • S3=8
 FF_SR
  • CK=1
  • D=1
  • Q=1
 HARD0
  • 0=1
 HARD1
  • 1=1
 IOB
  • I=1
  • O1=2
  • PAD=3
 IOB_IMUX
  • I=1
  • OUT=1
 IOB_INBUF
  • IN=1
  • OUT=1
 IOB_OUTBUF
  • IN=2
  • OUT=2
 IOB_PAD
  • PAD=3
 LUT5
  • A1=7
  • A2=3
  • A3=4
  • A4=3
  • A5=3
  • O5=35
 LUT6
  • A1=13
  • A2=14
  • A3=42
  • A4=45
  • A5=71
  • A6=73
  • O6=74
 PAD
  • PAD=3
 REG_SR
  • CE=2
  • CK=32
  • D=32
  • Q=32
 SLICEL
  • BX=3
  • BY=4
  • CE=18
  • CIN=22
  • CLK=18
  • COUT=22
  • F1=27
  • F2=8
  • F3=6
  • F4=6
  • G1=26
  • G2=9
  • G3=6
  • G4=6
  • SR=16
  • X=1
  • XB=2
  • XQ=15
  • Y=3
  • YQ=18
 SLICEL_C1VDD
  • 1=3
 SLICEL_C2VDD
  • 1=4
 SLICEL_CYMUXF
  • 0=25
  • 1=25
  • OUT=25
  • S0=25
 SLICEL_CYMUXG
  • 0=22
  • 1=22
  • OUT=22
  • S0=22
 SLICEL_F
  • A1=27
  • A2=8
  • A3=6
  • A4=6
  • D=27
 SLICEL_FFX
  • CE=15
  • CK=15
  • D=15
  • Q=15
  • SR=14
 SLICEL_FFY
  • CE=18
  • CK=18
  • D=18
  • Q=18
  • SR=16
 SLICEL_G
  • A1=26
  • A2=9
  • A3=6
  • A4=6
  • D=26
 SLICEL_GNDF
  • 0=22
 SLICEL_GNDG
  • 0=18
 SLICEL_XORF
  • 0=14
  • 1=14
  • O=14
 SLICEL_XORG
  • 0=14
  • 1=14
  • O=14
 SLICEX
  • A=4
  • A1=5
  • A2=5
  • A3=11
  • A4=12
  • A5=11
  • A6=11
  • AMUX=2
  • AQ=9
  • AX=1
  • B=1
  • B1=2
  • B2=2
  • B3=10
  • B4=11
  • B5=10
  • B6=11
  • BMUX=1
  • BQ=10
  • C=3
  • C1=2
  • C2=2
  • C3=8
  • C4=9
  • C5=9
  • C6=9
  • CE=1
  • CLK=10
  • CQ=6
  • D=2
  • D1=1
  • D2=1
  • D3=8
  • D4=8
  • D5=9
  • D6=9
  • DQ=7
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s200-tq144-4 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s200-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s200-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
Start 0 0 0 0 0 0 0
_impact 98 76 0 0 0 0 0
arwz 5 5 0 0 0 0 0
bitgen 777 772 0 0 0 0 0
edif2ngd 1 1 0 0 0 0 0
map 931 794 0 0 0 0 0
netgen 9 9 0 0 0 0 0
ngc2edif 3 3 0 0 0 0 0
ngcbuild 9 9 0 0 0 0 0
ngdbuild 1012 1001 0 0 0 0 0
obngc 9 9 0 0 0 0 0
par 790 785 3 0 0 0 0
trce 762 762 0 0 0 0 0
xst 1486 1377 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/pn_db_nsw_select_ip.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Constraints Editor PROP_intProjectCreationTimestamp=2015-02-04T17:31:27
PROP_intWbtProjectID=D4D675BE606849FC80D8810D46929BC7 PROP_intWbtProjectIteration=3
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=true PROP_DevFamily=Spartan3
PROP_DevDevice=xc3s200 PROP_DevFamilyPMName=spartan3
PROP_DevPackage=tq144 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDE=3 NGDBUILD_NUM_FDRE=29 NGDBUILD_NUM_FDSE=1
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_INV=9 NGDBUILD_NUM_LUT1=31 NGDBUILD_NUM_LUT2=5
NGDBUILD_NUM_LUT4=12 NGDBUILD_NUM_MUXCY=47 NGDBUILD_NUM_OBUF=2 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=28
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDE=3 NGDBUILD_NUM_FDRE=29 NGDBUILD_NUM_FDSE=1
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=9 NGDBUILD_NUM_LUT1=31
NGDBUILD_NUM_LUT2=5 NGDBUILD_NUM_LUT4=12 NGDBUILD_NUM_MUXCY=47 NGDBUILD_NUM_OBUF=2
NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=28
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s200-4-tq144 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=8
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5