Top Project Status (04/18/2015 - 08:34:08)
Project File: ADC_MCP3208_VarR_Cds_Dms.xise Parser Errors: No Errors
Module Name: Top Implementation State: Programming File Generated
Target Device: xc3s200-4tq144
  • Errors:
No Errors
Product Version:ISE 14.2
  • Warnings:
195 Warnings (1 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 191 3,840 4%  
Number of 4 input LUTs 643 3,840 16%  
Number of occupied Slices 408 1,920 21%  
    Number of Slices containing only related logic 408 408 100%  
    Number of Slices containing unrelated logic 0 408 0%  
Total Number of 4 input LUTs 733 3,840 19%  
    Number used as logic 643      
    Number used as a route-thru 90      
Number of bonded IOBs 7 97 7%  
Number of BUFGMUXs 2 8 25%  
Number of DCMs 2 4 50%  
Average Fanout of Non-Clock Nets 4.18      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentÅä 4 18 09:05:23 20150190 Warnings (0 new)4 Infos (0 new)
Translation ReportCurrentÅä 4 18 09:05:28 2015000
Map ReportCurrentÅä 4 18 09:05:32 201502 Warnings (1 new)4 Infos (0 new)
Place and Route ReportCurrentÅä 4 18 09:05:44 201503 Warnings (0 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentÅä 4 18 09:05:47 2015006 Infos (0 new)
Bitgen ReportCurrentÅä 4 18 09:05:51 2015002 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Date±Ý 4 17 08:39:22 2015
WebTalk ReportCurrentÅä 4 18 09:05:52 2015
WebTalk Log FileCurrentÅä 4 18 09:05:57 2015

Date Generated: 04/18/2015 - 09:26:20