top Project Status
Project File:	Switch.xise	Parser Errors:	No Errors
Module Name:	top	Implementation State:	Programming File Generated
Target Device:	xc3s200-4tq144	Errors:	No Errors
Product Version:	ISE 14.2	Warnings:	3 Warnings (3 new)
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	53	3,840	1%
Number of 4 input LUTs	35	3,840	1%
Number of occupied Slices	37	1,920	1%
Number of Slices containing only related logic	37	37	100%
Number of Slices containing unrelated logic	0	37	0%
Total Number of 4 input LUTs	66	3,840	1%
Number used as logic	35
Number used as a route-thru	31
Number of bonded IOBs	15	97	15%
Number of BUFGMUXs	1	8	12%
Average Fanout of Non-Clock Nets	2.36

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	格 4 16 17:53:04 2015	0	2 Warnings (2 new)	1 Info (0 new)
Translation Report	Current	格 4 16 17:53:09 2015	0	0	0
Map Report	Current	格 4 16 17:53:12 2015	0	0	2 Infos (0 new)
Place and Route Report	Current	格 4 16 17:53:17 2015	0	1 Warning (1 new)	2 Infos (0 new)
Power Report
Post-PAR Static Timing Report	Current	格 4 16 17:53:20 2015	0	0	6 Infos (2 new)
Bitgen Report	Current	格 4 16 17:53:23 2015	0	0	1 Info (1 new)

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	格 4 16 17:53:24 2015
WebTalk Log File	Current	格 4 16 17:53:29 2015

Date Generated: 04/18/2015 - 14:37:52