`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:01:06 02/11/2015 
// Design Name: 
// Module Name:    top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module test(
	input osc,
	inout Thermistor,
	input rxd,
	output txd
    );

//wire [31:0]PrintfData1;
//wire [31:0]PrintfData2;
//wire [31:0]PrintfData3;
//wire [31:0]PrintfData4;
//wire [31:0]PrintfData5;
	 
wire [7:0]sec;
wire [7:0]minute;
wire [7:0]hour;
reg [1:0]reset_cnt = 0;
reg reset = 1'b1;
wire [31:0]PrintfData1;
always@(posedge osc)
begin
	if(reset==1'b1)
	begin
	reset_cnt <= reset_cnt + 1'b1;
	end 
   if(reset_cnt==2)
	begin
	reset <= 1'b0;
	end
end 

reg [7:0]cnt = 8'd0;
reg clk_main = 0;
//reg clk_main2 = 0;
//always@(posedge osc)
//begin
//	if(reset==1'b1)
//	begin
//	cnt <= 8'd0;
//	clk_main <= 1'b0;
//	end 
//	else
//	begin
//		if(cnt >= 8'd2)
//		begin
//			cnt <= 8'd0;
//			clk_main <= ~clk_main;
//		end
//		else cnt <= cnt + 1'b1;
//	end
//end 
//always@(posedge osc)
//clk_main <= osc;
//wire clk_main2;
//assign clk_main2 = clk_main;
USB Printf
(
	.clk_main(osc),   
	.reset(reset),	 
	.RXD(rxd),
	.TXD(txd),
	.PrintfData1(PrintfData1[30:0])
);
Thermistor DS18B20
(
	.clk_main(osc),   
	.reset(reset),	 
	.Thermistor2(Thermistor),
	.PrintfData4(PrintfData1)
);
endmodule