module test(
	input osc,
	output reg [7:0]LED,
	input SW_INPUT0,
	input SW_INPUT1,
	input SW_INPUT2,
	output reg SW_COMMON0,
	output reg SW_COMMON1,
	output reg SW_COMMON2
    );
reg [1:0]reset_cnt = 0;
reg reset_main = 1'b1;
always@(posedge osc)
begin
if(reset_main==1'b1)
begin
reset_cnt <= reset_cnt + 1'b1;
end 
if(reset_cnt==2)
begin
reset_main <= 1'b0;
end
end 

reg [31:0]cnt_sw = 0;
wire tick;
reg ff_tick=0;
always@(posedge ff_tick or posedge osc)
begin
  if(ff_tick == 1'b1)
	begin
	cnt_sw <= 32'd0;
	end
	else cnt_sw <= cnt_sw +1'b1;
end 
assign tick = (cnt_sw==32'd5000)? 1'b1: 1'b0;


always@(posedge osc)
begin
	ff_tick <=tick;
end 

reg [2:0]sw_column=0;
always@(posedge ff_tick or posedge reset_main)
begin
	if(reset_main==1'b1)
	begin
	sw_column <= 32'd0;
	end 
	else if(sw_column==4)
	begin
		sw_column <= 3'd1;
	end 
	else sw_column <= sw_column + 1'b1;

end 
always@(posedge osc or posedge reset_main)
begin
	if(reset_main==1'b1)
	begin
		SW_COMMON0 <=  1'b0;
		SW_COMMON1 <=  1'b0;
		SW_COMMON2 <=  1'b0;
	end
	else
	begin
		case(sw_column)
		1:
		begin
			SW_COMMON0 <=  1'b0;
			SW_COMMON1 <=  1'b1;
			SW_COMMON2 <=  1'b1;
		end 
		2:
		begin
			SW_COMMON0 <=  1'b1;
			SW_COMMON1 <=  1'b0;
			SW_COMMON2 <=  1'b1;
		end
		3:
		begin
			SW_COMMON0 <=  1'b1;
			SW_COMMON1 <=  1'b1;
			SW_COMMON2 <=  1'b0;
		end 
		endcase
	end
end 
reg [2:0]ff_sw = 0;
always@(posedge osc or posedge reset_main)
begin
	if(reset_main)
	begin
		ff_sw <= 3'd0;
	end
	else ff_sw<={SW_INPUT2,SW_INPUT1,SW_INPUT0};
end 

always@(posedge osc or posedge reset_main)
begin
	if(reset_main)
	begin
		LED[7:0] =8'd0;
	end
	else
	begin
		case(sw_column)
		1: 
		begin
			case(ff_sw)
			3'b110:LED[2:0] = 3'b001;
			3'b101:LED[2:0] = 3'b010;
			3'b011:LED[2:0] = 3'b100;
			default: LED[2:0] =3'b000; 
			endcase		
		end 
		2: 
		begin
			case(ff_sw)
			3'b110:LED[5:3] = 3'b001; 
			3'b101:LED[5:3] = 3'b010; 
			3'b011:LED[5:3] =3'b100; 
			default: LED[5:3] = 3'b000; 
			endcase
		end 
		3:
		begin
			case(ff_sw)
			3'b110:LED[7:5] = 3'b001;
			3'b101:LED[7:5] = 3'b010;
			3'b011:LED[7:5] = 3'b100; 
			default:LED[7:5] =3'b000; 
			endcase
		end 
		default: LED[7:0] =8'd0;
		endcase
	end 
end 

endmodule