`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:39:13 02/04/2015 
// Design Name: 
// Module Name:    top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module test(
	input clk,
	output reg STEPMotor_DIR,
	output reg STEPMotor_CLK
    );

reg [16:0] cnt = 0;
reg [27:0] cnt_dir = 0;
wire stop_flag;
reg [1:0]reset_cnt = 0;
reg reset = 1'b1;
always@(posedge clk)
begin
	if(reset==1'b1)
	begin
	reset_cnt <= reset_cnt + 1'b1;
	end 
   if(reset_cnt==2)
	begin
	reset <= 1'b0;
	end
end 
always@(posedge clk)
begin
	if(reset == 1'b1)
	begin
		STEPMotor_CLK <= 1'b0;
	end
	else if(cnt == 17'd100000) //pulse duty width variable value! 
	begin
		STEPMotor_CLK <= (~STEPMotor_CLK & stop_flag);
		cnt <= 17'd0;
	end 
	else cnt <= cnt + 1'b1;
end 

always@(posedge clk)
begin
	if(reset == 1'b1)
	begin
		STEPMotor_DIR <= 1'b0;
	end
	else if(cnt_dir == 28'd250000000) //5초 
	begin
		STEPMotor_DIR <= ~STEPMotor_DIR;
		cnt_dir <= 28'd0;
	end 
	else cnt_dir <= cnt_dir + 1'b1;
end 

assign stop_flag = (cnt_dir>32'd200000000)? 1'b0: 1'b1; //4초 


//assign STEPMotor_DIR = 1'b1; //test code!

endmodule