`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:34:15 02/12/2015 
// Design Name: 
// Module Name:    top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module test(
	input osc,
	input UltraSonic_InPulse,
	output UltraSonic_OutPulse,
	output lcd_rs,
	output lcd_en,
	output [7:0]lcd_data
    );
	 

wire [31:0]echo_cnt;
reg [1:0]reset_cnt = 0;
reg reset = 1'b1;
reg UltraSonic_InPulse_r = 0;
reg UltraSonic_InPulse_r2 = 0;
reg UltraSonic_InPulse_r3 = 0;	 
wire UltraSonic_InPulse_real;

always@(posedge clk_main)
UltraSonic_InPulse_r <= UltraSonic_InPulse;
always@(posedge clk_main)
UltraSonic_InPulse_r2 <= UltraSonic_InPulse_r;
always@(posedge clk_main)
UltraSonic_InPulse_r3 <= UltraSonic_InPulse_r2;

assign UltraSonic_InPulse_real = (UltraSonic_InPulse_r & UltraSonic_InPulse_r2 & UltraSonic_InPulse_r3);
always@(posedge osc)
begin
	if(reset==1'b1)
	begin
	reset_cnt <= reset_cnt + 1'b1;
	end 
	if(reset_cnt==2)
	begin
	reset <= 1'b0;
	end
end 

SR04_Sensor Ultrasonic
(
	.clk(osc),   
	.reset(reset),	 
	.UltraSonic_OutPulse(UltraSonic_OutPulse),
	.UltraSonic_InPulse(UltraSonic_InPulse_real),
	.echo_cnt(echo_cnt)
);
LCD TLCD
(
	.clk(osc),
	.reset(reset),
	.rs(lcd_rs),
	.en(lcd_en),
	.data(lcd_data),
	.echo_cnt(echo_cnt)
);
endmodule