`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:06:55 02/12/2015 
// Design Name: 
// Module Name:    top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module test(
	input osc,
	output rs,
	output en,
	output [7:0]data,
	output RTC_SCL,
	inout RTC_SDA
    );
	 
reg [1:0]reset_cnt = 0;
reg reset = 1'b1;
wire clk_main;
wire clk_fb, clk_fb2;
always@(posedge osc)
begin
	if(reset==1'b1)
	begin
	reset_cnt <= reset_cnt + 1'b1;
	end 
	if(reset_cnt==2)
	begin
	reset <= 1'b0;
	end
end 	 
wire [7:0]sec;
wire [7:0]minute;
wire [7:0]hour;
LCD TLCD
(
	.clk(osc),
	.reset(reset),
	.rs(rs),
	.en(en),
	.data(data),
	.hour(hour),
	.minute(minute),
	.sec(sec)
);
I2C RTC1307
(
	.clk(osc),
	.reset(reset),
	.scl(RTC_SCL),
	.sda(RTC_SDA),
	.hour(hour),
	.minute(minute),
	.sec(sec)
 );
endmodule