`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:40:00 04/18/2014 
// Design Name: 
// Module Name:    hextobcd 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module hextobcd(
    input [30:0] hex,
    output [39:0] bcdout
    );

reg [30:0] bin;
reg [39:0] result;
always @(hex)
begin
    bin = hex;
    result = 0;
    repeat(30)
    begin
        result[0] = bin[30];
        if(result[3:0] > 4)
            result[3:0] = result[3:0] + 4'd3;
        if(result[7:4] > 4)
            result[7:4] = result[7:4] + 4'd3;
        if(result[11:8] > 4)
            result[11:8] = result[11:8] + 4'd3;
        if(result[15:12] > 4)
            result[15:12] = result[15:12] + 4'd3;
        if(result[19:16] > 4)
            result[19:16] = result[19:16] + 4'd3;
        if(result[23:20] > 4)
            result[23:20] = result[23:20] + 4'd3;
        if(result[27:24] > 4)
            result[27:24] = result[27:24] + 4'd3;
        if(result[31:28] > 4)
            result[31:28] = result[31:28] + 4'd3;
        if(result[35:32] > 4)
            result[35:32] = result[35:32] + 4'd3;
				
        result = result << 1; //0~30으로 데이터 배열이 이동함
        bin = bin << 1; //30~0으로 데이터 패킷이 이동하면서 result로 대입
    end
    result[0] = bin[30];
end

assign bcdout = result;

endmodule