`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:28:06 11/22/2014 
// Design Name: 
// Module Name:    SpiCom 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module SpiCom(
    input clk,                   // main clock
    input clk_spi,               // spi clock 4MHz
    output sclk,
    output cs,
    output mosi,
    input miso,
	 output [31:0]PrintfData1,
	 output [31:0]PrintfData2,
	 output [31:0]PrintfData3
    );
reg [23:0] spi_ir1=0;
reg [7:0] spi_ir2;




wire [23:0] spi_data_r;
reg [23:0] VarialbleR_f = 0;
reg [23:0] Cds_f = 0;
reg [23:0] Dms_f = 0;
parameter VarialbleR_ch =  24'h060000;
parameter Cds_ch = 24'h064000;
parameter Dms_ch = 24'h068000;

reg spi_start1 = 0, spi_start2 = 0;
wire spi_done1, spi_done2;
reg [31:0] reset_counter = 0;
//wire [11:0]data_r;
// spi sequencer
parameter S0=0, S1=1, S2=2, S3=3, S4=4, S5=5, S6=6, S7=7, S8=8, S9=9, S10=10, S11=11, S12=12, S13=13;
reg [3:0] state_spi = S0;
reg [2:0]adc_cnt = 0;

assign PrintfData1 = VarialbleR_f;
assign PrintfData2 = Cds_f;
assign PrintfData3 = Dms_f;
/////////////////////////////////////////////////////////////////////
// reset generation
/////////////////////////////////////////////////////////////////////
//always @(posedge clk_main)
//begin
//    if(reset_main == 1'b1)
//        reset_cnt <= reset_cnt + 1;
//    if(reset_cnt == 2)
//        reset_main <= 1'b0;
//end
//
///////////////////////////////////////////////////////////////////////
// SPI sequencer
/////////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
    case(state_spi)
        S0:
        begin
			reset_counter <= reset_counter + 1;
			if(reset_counter == 50)
			begin
				state_spi <= S1;
				reset_counter <= 32'd0;
				adc_cnt <= 1'b0;
				VarialbleR_f <=  24'd0;
				Cds_f <= 24'd0;
				spi_ir1 <= 24'd0;
				adc_cnt <= 3'd0;
			end 
        end
        S1: //start
				begin
				reset_counter <= reset_counter + 1;
				if(reset_counter == 500)
					begin
					state_spi <= S2;
					reset_counter <= 32'd0;
					if(adc_cnt == 3'd3)
					begin
					adc_cnt <= 3'd0;
					end
					else adc_cnt <= adc_cnt + 1'b1;	
					end 
				end
		  S2: //start
			begin
				case(adc_cnt)
				1: spi_ir1 <= VarialbleR_ch;
				2: spi_ir1 <= Cds_ch;
				3: spi_ir1 <= Dms_ch;
				endcase
            state_spi <= S3;
			end
        S3:
        begin
            spi_start1 <= 1;
            state_spi <= S4;
        end
		   S4:
			begin
				spi_start1 <= 0;
			   state_spi <= S5;
			end 
        S5:
			begin
				//spi_start1 <= 0;
				if(spi_done1)
				begin
						if(adc_cnt == 3'd1)
						begin
							VarialbleR_f <= spi_data_r&24'h000fff;
						end 
						else if(adc_cnt == 3'd2)
						begin
							Cds_f <= spi_data_r&24'h000fff;
						end 
						else if(adc_cnt == 3'd3)
						begin
							Dms_f <= spi_data_r&24'h000fff;
						end 
						state_spi <= S1;
				end
			end
    endcase
end
ADC SpiModule
(
  .clk(clk),                  // main clock
  .clk_spi(clk_spi),               // spi clock 4MHz
  .data_w(spi_ir1),
  .data_r(spi_data_r),
  .start(spi_start1),
  .done(spi_done1),	
  .sclk(sclk),
  .cs(cs),
  .mosi(mosi),
  .miso(miso)
 );
 
endmodule