{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1532001716270 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 Patches 0.01we SJ Web Edition " "Version 15.0.0 Build 145 04/22/2015 Patches 0.01we SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1532001716276 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 19 21:01:56 2018 " "Processing started: Thu Jul 19 21:01:56 2018" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1532001716276 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1532001716276 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off test -c test " "Command: quartus_eda --read_settings_files=off --write_settings_files=off test -c test" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1532001716276 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "test_8_1200mv_85c_slow.vo D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/ simulation " "Generated file test_8_1200mv_85c_slow.vo in folder \"D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1532001716986 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "test_8_1200mv_0c_slow.vo D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/ simulation " "Generated file test_8_1200mv_0c_slow.vo in folder \"D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1532001716995 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "test_min_1200mv_0c_fast.vo D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/ simulation " "Generated file test_min_1200mv_0c_fast.vo in folder \"D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1532001717005 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "test.vo D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/ simulation " "Generated file test.vo in folder \"D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1532001717015 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "test_8_1200mv_85c_v_slow.sdo D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/ simulation " "Generated file test_8_1200mv_85c_v_slow.sdo in folder \"D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1532001717024 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "test_8_1200mv_0c_v_slow.sdo D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/ simulation " "Generated file test_8_1200mv_0c_v_slow.sdo in folder \"D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1532001717033 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "test_min_1200mv_0c_v_fast.sdo D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/ simulation " "Generated file test_min_1200mv_0c_v_fast.sdo in folder \"D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1532001717043 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "test_v.sdo D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/ simulation " "Generated file test_v.sdo in folder \"D:/Product/FPGA/Altera/LK-EP6C-FT/Code/renewal/RS232/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1532001717052 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4739 " "Peak virtual memory: 4739 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1532001717088 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 19 21:01:57 2018 " "Processing ended: Thu Jul 19 21:01:57 2018" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1532001717088 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1532001717088 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1532001717088 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1532001717088 ""}