`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:06:32 02/04/2015 
// Design Name: 
// Module Name:    top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module test(
	input osc,
	output reg [7:0]SEG,
	output [3:0]CA
    );

parameter char_0 = 8'h3F;
parameter char_1 = 8'h06;
parameter char_2 = 8'h5B;
parameter char_3 = 8'h4F;
parameter char_4 = 8'h66;
parameter char_5 = 8'h6D;
parameter char_6 = 8'h7D;
parameter char_7 = 8'h27;
parameter char_8 = 8'h7F;
parameter char_9 = 8'h6F;

wire [39:0] bcd1;
	 
reg [32:0] cnt = 0;   // ?Hz 분주용
reg [15:0] cnt_1000 = 0;   // ?Hz 분주용
reg start_buf = 0;   // 입력 스위치의 토글을 위한 버퍼
reg continue = 0;    // 토글을 받아서 계속할찌 안할지 결정
reg  toggle =0;    // 토글 기존 값저장
reg c100hz = 0;    // ?Hz 분주되었을때 나갈 스위치
reg c1000hz = 0;    // ?Hz 분주되었을때 나갈 스위치
reg c1hz = 0;    // ?Hz 분주되었을때 나갈 스위치
reg [4:0] value = 0;   // 7-Segment 로 받는 값
reg [7:0] seg_buf = 0;  // 7-Segment 나갈 값
reg [3:0] an_buf = 0;  // 4개의 LED 주소값
reg comm = 0;     //common cathode 제어 
reg sta =0;

wire [7:0]num_1000_w;
wire [7:0]num_100_w;
wire [7:0]num_10_w;
wire [7:0]num_1_w;

reg [7:0]num_1000 =0;
reg [7:0]num_100 =0;
reg [7:0]num_10 =0;
reg [7:0]num_1 =0;

reg [13:0] fnd_cnt =0;

reg [7:0]data = 0;
reg [15:0]sec =0;
reg [22:0]sec_cnt =0;
reg [3:0]digit = 1;
wire tc;
wire tc2;
reg [1:0]reset_cnt = 0;
reg reset = 1'b1;
always@(posedge osc)
begin
	if(reset==1'b1)
	begin
	reset_cnt <= reset_cnt + 1'b1;
	end 
   if(reset_cnt==2)
	begin
	reset <= 1'b0;
	end
end 

 always@(posedge osc or posedge reset)begin   // 클럭분주
	if(reset)
	begin
			cnt_1000 <= 16'd0;
	end 
	else if (cnt_1000 == 16'd50000)  //1mSec
		begin
			cnt_1000 <= 16'd0;
		end
	else
		begin
			cnt_1000 <= cnt_1000 + 1'b1;
		end
 end
 always@(posedge osc or posedge reset)
 begin
	if(reset)
	begin
		sec_cnt <= 32'd0;
	end
 	else if (sec_cnt == 5000000) // 100mSec 
	begin 
	sec_cnt <= 32'd0;
	end
	else begin
	sec_cnt <= sec_cnt + 1'b1;	
	end
 
 end 
assign tc = (sec_cnt == 23'd5000000)?1'b1:1'b0;
assign tc2 = (cnt_1000 == 16'd50000)?1'b1:1'b0;

 always@(posedge osc or posedge reset)
 begin 
	if(reset)
	begin
		fnd_cnt<= 14'd0; 
	end 
	else if(fnd_cnt==16'd9999)
		begin 	
		fnd_cnt<= 14'd0; 
		end 
	else if(tc == 1'b1)
		begin
		fnd_cnt<=fnd_cnt+1'b1;
		end
 end 
 
 always@(posedge osc or posedge reset)
 begin
 	if(reset)
	begin
		digit <= 4'd1;
	end
	else if(tc2 == 1'b1)
	begin
		if(digit == 4'd8)
		begin
			digit <= 4'd1;
		end 
		else digit <= (digit<<1'b1);
	end 
 end 
 
reg [7:0]segment_r = 0;
always@(posedge osc)
begin
	if(reset)SEG <= 8'd0;
	else SEG <= segment_r;
end 
always@(*)
begin
	case(digit)
	4'd1: begin segment_r = num_1000;end
	4'd2: begin segment_r = num_100;end
	4'd4: begin segment_r = num_10;end
	4'd8: begin segment_r = num_1;end
	default : begin segment_r = 8'd0;end 
	endcase
end 	

always@(*)
begin
	case(num_1000_w)
	0: begin num_1000 = char_0;end
	1: begin num_1000 = char_1;end
	2: begin num_1000 = char_2;end
	3: begin num_1000 = char_3;end
	4: begin num_1000 = char_4;end
	5: begin num_1000 = char_5;end
	6: begin num_1000 = char_6;end
	7: begin num_1000 = char_7;end
	8: begin num_1000 = char_8;end
	9: begin num_1000 = char_9;end
	default : begin num_1000 = 8'd0;end 
	endcase
end 
always@(*)
begin	
	case(num_100_w)
	0: begin num_100 = char_0;end
	1: begin num_100 = char_1;end
	2: begin num_100 = char_2;end
	3: begin num_100 = char_3;end
	4: begin num_100 = char_4;end
	5: begin num_100 = char_5;end
	6: begin num_100 = char_6;end
	7: begin num_100 = char_7;end
	8: begin num_100 = char_8;end
	9: begin num_100 = char_9;end
	default : begin num_100 = 8'd0;end 
	endcase
end 	
always@(*)
begin	
	case(num_10_w)
	0: begin num_10 = char_0;end
	1: begin num_10 = char_1;end
	2: begin num_10 = char_2;end
	3: begin num_10 = char_3;end
	4: begin num_10 = char_4;end
	5: begin num_10 = char_5;end
	6: begin num_10 = char_6;end
	7: begin num_10 = char_7;end
	8: begin num_10 = char_8;end
	9: begin num_10 = char_9;end
	default : begin num_10 = 8'd0;end 
	endcase
end
always@(*)
begin	
	case(num_1_w)
	0: begin num_1	=	char_0;end
	1: begin num_1	=	char_1;end
	2: begin num_1	=	char_2;end
	3: begin num_1	=	char_3;end
	4: begin num_1	=	char_4;end
	5: begin num_1	=	char_5;end
	6: begin num_1	=	char_6;end
	7: begin num_1	=	char_7;end
	8: begin num_1	=	char_8;end
	9: begin num_1	=	char_9;end
	default : begin num_1 = 8'd0; end
	endcase
end


assign num_1000_w = bcd1[15:12];
assign num_100_w = bcd1[11:8];
assign num_10_w = bcd1[7:4];
assign num_1_w = bcd1[3:0];
assign CA = digit;

hextobcd hextobcd1
(
	.hex({17'd0,fnd_cnt[13:0]}),
 //.hex(Init_OFFTIME[30:0]),
   .bcdout(bcd1)
);

endmodule 