`timescale 1ns / 1ps
//////////SW_COMMON0
////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:31:51 02/04/2015 
// Design Name: 
// Module Name:    top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module test(
	input clk,
	output  DCMotor_CCW_SIG,
	output  DCMotor_CW_SIG
    );
reg DCMotor_CCW_SIG_r;
reg DCMotor_CW_SIG_r;
reg [27:0] cnt = 0;
wire stop_flag;

reg [1:0]reset_cnt = 0;
reg reset = 1'b1;
always@(posedge clk)
begin
	if(reset==1'b1)
	begin
	reset_cnt <= reset_cnt + 1'b1;
	end 
   if(reset_cnt==2)
	begin
	reset <= 1'b0;
	end
end 

always@(posedge clk)
begin
	if(reset == 1'b1)
	begin
		DCMotor_CCW_SIG_r <=1'b1;
		DCMotor_CW_SIG_r <=1'b0;
	end
	else if(cnt == 28'd250000000) //5초 
	begin
		cnt <= 28'd0;
		DCMotor_CCW_SIG_r <= ~DCMotor_CCW_SIG_r;
		DCMotor_CW_SIG_r <= ~DCMotor_CW_SIG_r; 

	end 
	else cnt <= cnt + 1'b1;
end 

assign stop_flag = (cnt>32'd200000000)? 1'b0: 1'b1; //4초 
assign DCMotor_CCW_SIG=DCMotor_CCW_SIG_r&stop_flag;
assign DCMotor_CW_SIG=DCMotor_CW_SIG_r&stop_flag;

endmodule