# Reading C:/altera/15.0/modelsim_ae/tcl/vsim/pref.tcl
# do test_run_msim_gate_verilog.do
# if {[file exists gate_work]} {
# 	vdel -lib gate_work -all
# }
# vlib gate_work
# vmap work gate_work
# Model Technology ModelSim PE vmap 10.3d Lib Mapping Utility 2014.10 Oct  7 2014
# vmap -modelsim_quiet work gate_work 
# Copying C:/altera/15.0/modelsim_ae/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied C:/altera/15.0/modelsim_ae/win32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
# 
# vlog -vlog01compat -work work +incdir+. {test.vo}
# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 14:38:05 on Jul 19,2018
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+." test.vo 
# -- Compiling module test
# 
# Top level modules:
# 	test
# End time: 14:38:05 on Jul 19,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
